Description
When EUSCIB is configured as I2C Master with the external UCLKI as clock source, the
UCLKI signal is not available and cannot be used to source I2C clock.
Workaround
Use LFXTCLK via ACLK or HFXTCLK via SMCLK as clock source (BRCLK) for I2C in
master mode with external clock source.
USCI37
USCI Module
Category
Functional
Function
Reading RXBUF during an active I2C communication might result in unintended bus
stalls.
Description
The falling edge of SCL bus line is used to set an internal RXBUF-written flag register,
which is used to detect a potential RXBUF overflow. If this flag is cleared with a read
access from the RXBUF register during a falling edge of SCL, the clear condition might be
missed. This could result in an I2C bus stall at the next received byte.
Workaround
(1) Execute two consecutive reads of RXBUF, if t
SCL
> 4 x t
MCLK
.
or
(2) Provoke an I2C bus stall before reading RXBUF. A bus stall can be verified by
checking if the clock line low status indicator bit UCSCLLOW is set for at least three USCI
bit clock cycles i.e. 3 x t
BitClock
.
USCI41
USCI Module
Category
Functional
Function
UCBUSY bit of eUSCIA module might not work reliable when device is in SPI mode.
Description
When eUSCIA is configured in SPI mode, the UCBUSY bit might get stuck to 1 or start
toggling after transmission is completed. This happens in all four combinations of Clock
Phase and Clock Polarity options (UCAxCTLW0.UCCKPH & UCAxCTLW0.UCCKPL bits)
as well as in Master and Slave mode. There is no data loss or corruption. However the
UCBUSY cannot be used in its intended function to check if transmission is completed.
Because the UCBUSY bit is stuck to 1 or toggles, the clock request stays enabled and
this adds additional current consumption in low power mode operation.
Workaround
For correct functional implementation check on transmit or receive interrupt flag
UCTXIFG/UCRXIFG instead of UCBUSY to know if the UCAxTXBUF buffer is empty or
ready for the next complete character.
To reduce the additional current it is recommended to either reset the SPI module
(UCAxCTLW0.UCSWRST) in the UCBxCTLW0 or send a dummy byte 0x00 after the
intended SPI transmission is completed.
USCI42
USCI Module
Category
Functional
Function
UART asserts UCTXCPTIFG after each byte in multi-byte transmission
Description
UCTXCPTIFG flag is triggered at the last stop bit of every UART byte transmission,
independently of an empty buffer, when transmitting multiple byte sequences via UART.
The erroneous UART behavior occurs with and without DMA transfer.
Workaround
None.
Advisory Descriptions
22
MSP430F6735A Microcontroller
SLAZ647S – FEBRUARY 2015 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
