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Texas Instruments LP876242-Q1, User Manual

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Texas Instruments LP876242-Q1 User Manual Download Page 15

Figure 5-6. Layout Signal, Layer 4

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Schematic, Layout, and Bill of Materials

SLVUC20A – MARCH 2021 – REVISED AUGUST 2022

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LP876242-Q1 Evaluation Module

15

Copyright © 2022 Texas Instruments Incorporated

Summary of Contents for LP876242-Q1

Page 1: ...5 Schematic Layout and Bill of Materials 10 6 Additional Resources 23 7 Revision History 23 List of Figures Figure 2 1 EVM Top View 3 Figure 3 1 EVM Header J18 5 Figure 3 2 EVM Bottom Side 7 Figure 4 1 Interface Settings for I2C Communication 9 Figure 5 1 Main Schematic Page 10 Figure 5 2 MCU Schematic Page 11 Figure 5 3 Layout Top Layer 1 12 Figure 5 4 Layout Ground Layer 2 13 Figure 5 5 Layout S...

Page 2: ...f Materials 18 Trademarks All trademarks are the property of their respective owners Trademarks www ti com 2 LP876242 Q1 Evaluation Module SLVUC20A MARCH 2021 REVISED AUGUST 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 3: ...the following steps 1 Connect power to the EVM 2 Connect the EVM to the host PC through the USB In the event that the power is provided by the USB cable apply the appropriate jumper connection to connect VBUS and VCCA see Table 3 5 3 Launch the GUI and evaluate Terminal J7 labeled VCCA in Figure 2 1 can accept wire gauges up to 14 AWG The voltage supplied must be within the input range of the devi...

Page 4: ...up to 14 AWG Table 3 1 lists the terminal blocks found around the perimeter of the EVM J7 VCCA is the input voltage for the regulators The rest of the terminal blocks are for the BUCK outputs Table 3 1 Terminal Blocks Terminal Designator Description VCCA J7 All Regulator Input 2 8 V to 5 5 V Range BUCK1 J8 Buck 1 Output 2 A Capable BUCK2 J10 Buck 2 Output 4 A Capable BUCK3 J12 Buck 3 Output 3 A Ca...

Page 5: ...PMIC is in the Alternative function and the I2C mode is selected This setting is also done on connector J24 by closing GPIO2 to SCL2 CS if I2C2 is wanted to be used SPI mode J18 VIO I2C SPI Closed SPI mode Chip Select GPIO2 and GPIO3 supports SPI communication when the PMIC is in the Alternative function This setting is also done on connector J24 by closing GPIO2 to SCL2 CS if I2C2 is wanted to be...

Page 6: ...A Watchdog mode GPIO2 and GPIO3 supports the Q A Watchdog when the PMIC is in Alternative function and the I2C mode selected This setting is also done on connector J18 by closing GPIO3 to SDA2 SDO if I2C2 is wanted to be used SPI mode J18 SPI_EN Closed SPI mode Chip Select GPIO2 and GPIO3 supports SPI communication when the PMIC is in the Alternative function This setting is also done on connector...

Page 7: ... DIP Switches There are three DIP switches S1 S2 and S3 on the back side of the PCB S1 switch can be used for configuring chip select for target device in multi PMIC stacked use case S2 and S3 switches allow the user to disconnect the level shifter from the PMIC GPIOs or serial interfaces The level shifter has pull ups on the MCU side that can cause unwanted high state on the GPIO signals if confi...

Page 8: ...es are available for supplying VIO for the PMIC selectable from J33 Two SN74GTL2003 level shifters U4 U6 are used in order to support the use case of the PMIC VIO of 1 8 V the MCU IO is 3 3 V In addition to the level shifters the TS3A5018RSVR U8 switch is used to apply the pullup voltages to the I2C lines only when the EVM is configured as controller J17 Additional TS3A5018RSVR U9 switch is used f...

Page 9: ...jumpers from J18 J24 as highlighted in red in Figure 4 1 At J18 the jumper on SPI_EN connects the microcontroller to the SPI bus to which the PMIC is connected The SPI does not have a device ID and therefore the chip select is used to determine which PMIC receives and responds to commands on the SPI bus Figure 4 1 Interface Settings for I2C Communication www ti com Customization SLVUC20A MARCH 202...

Page 10: ...aterials Figure 5 1 Main Schematic Page Schematic Layout and Bill of Materials www ti com 10 LP876242 Q1 Evaluation Module SLVUC20A MARCH 2021 REVISED AUGUST 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 11: ...MCU Schematic Page www ti com Schematic Layout and Bill of Materials SLVUC20A MARCH 2021 REVISED AUGUST 2022 Submit Document Feedback LP876242 Q1 Evaluation Module 11 Copyright 2022 Texas Instruments Incorporated ...

Page 12: ...Layout Top Layer 1 Schematic Layout and Bill of Materials www ti com 12 LP876242 Q1 Evaluation Module SLVUC20A MARCH 2021 REVISED AUGUST 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 13: ...ayout Ground Layer 2 www ti com Schematic Layout and Bill of Materials SLVUC20A MARCH 2021 REVISED AUGUST 2022 Submit Document Feedback LP876242 Q1 Evaluation Module 13 Copyright 2022 Texas Instruments Incorporated ...

Page 14: ...ayout Signal Layer 3 Schematic Layout and Bill of Materials www ti com 14 LP876242 Q1 Evaluation Module SLVUC20A MARCH 2021 REVISED AUGUST 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 15: ...ayout Signal Layer 4 www ti com Schematic Layout and Bill of Materials SLVUC20A MARCH 2021 REVISED AUGUST 2022 Submit Document Feedback LP876242 Q1 Evaluation Module 15 Copyright 2022 Texas Instruments Incorporated ...

Page 16: ...ayout Ground Layer 5 Schematic Layout and Bill of Materials www ti com 16 LP876242 Q1 Evaluation Module SLVUC20A MARCH 2021 REVISED AUGUST 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 17: ...ayout Bottom Layer 6 www ti com Schematic Layout and Bill of Materials SLVUC20A MARCH 2021 REVISED AUGUST 2022 Submit Document Feedback LP876242 Q1 Evaluation Module 17 Copyright 2022 Texas Instruments Incorporated ...

Page 18: ...0 C63 C67 C70 C72 C74 C98 C99 C101 C102 C105 C108 C109 C117 C120 GCM155R71C104KA 55D 23 0 1uF MuRata CAP CERM 0 1 uF 16 V 10 X7R 0402 0402 7 C15 C42 C59 C66 GCM188D70J106ME 36D 4 Murata Chip Multilayer Ceramic Capacitors for Automotive 0603 8 C16 C17 C21 C35 C43 C44 C45 C48 C76 C85 C86 C90 GCM21BD70J226ME 36L 12 22uF MuRata CAP CERM 22 uF 6 3 V 20 X7T AEC Q200 Grade 1 0805 0805 9 C29 C55 C62 C69 G...

Page 19: ...d TH Header 2 54mm 3x1 TH 20 J7 J8 J10 J12 J14 1792863 5 Phoenix Contact Terminal Block 5mm 2x1 R A TH Terminal Block 5mm 2x1 R A TH 21 J18 J19 J22 J23 J24 J27 TSW 110 07 G S 6 Samtec Header 100mil 10x1 Gold TH 10x1 Header 22 J20 J21 J25 J26 TSW 102 07 G S 4 Samtec Header 100mil 2x1 Gold TH 2x1 Header 23 J28 J29 ESQ 111 14 T S 2 Samtec Conn Elevated Socket SKT 11 POS 2 54mm Solder ST Thru Hole Tub...

Page 20: ...R44 R45 R46 R47 R48 R49 R55 R56 R57 R58 R59 R60 R61 R62 R66 R73 R75 R76 R79 CRCW040210K0JNE D 34 10k Vishay Dale RES 10 k 5 0 063 W AEC Q200 Grade 0 0402 0402 33 R12 R14 R16 R69 R78 CRCW04021K20JNE D 5 1 2k Vishay Dale RES 1 2 k 5 0 063 W AEC Q200 Grade 0 0402 0402 34 R18 CRCW0402240RJNE D 1 240 Vishay Dale RES 240 5 0 063 W AEC Q200 Grade 0 0402 0402 35 R31 R70 R71 R74 R77 CRCW04021K00JNE D 5 1 0...

Page 21: ...tone Test Point Compact SMT Testpoint_Keystone_C ompact 45 U1 LP876242B0RQKRQ1 1 Texas Instruments Four 8 8 MHz Buck Converters for AWR and IWR MMICs VQFN HR32 46 U2 LM2901AVQPWRQ1 1 Texas Instruments AEC Q100 Quad Comparator PW0014A TSSOP 14 PW0014A 47 U3 MSP432E401YTPDT R 1 Texas Instruments MSP432E401YTPDT PDT0128A TQFP 128 PDT0128A 48 U4 U6 SN74GTL2003PWR 2 Texas Instruments 8 BIT BIDIRECTIONA...

Page 22: ...xas Instruments 0 5Ω Dual SPDT Bidirectional Analog Switch RSW0010A UQFN 10 RSW0010A 54 U12 TLV73333PQDRVRQ 1 1 Texas Instruments Capacitor Free 300 mA Low Dropout Regulator for Automotive DRV0006A WSON 6 DRV0006A 55 U13 TLV73318PQDRVRQ 1 1 Texas Instruments Capacitor Free 300 mA Low Dropout Regulator for Automotive DRV0006A WSON 6 DRV0006A 56 Y1 NX3225SA 25 000M STD CRS 2 1 NDK CRYSTAL 25 0000MHZ...

Page 23: ...ed buck output voltage sense points in Table 3 2 4 Updated the Figure 3 1 and header numbering in the corresponding description as well as in Table 3 3 changed header numbering in Table 3 4 4 Updated the header numbering Figure 3 2 capacitors numbering in Table 3 6 updated the dip switches description in Table 3 7 6 Updated the header numbering and IC names for supplying power to the MCU updated L...

Page 24: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 25: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 26: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 27: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 28: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 29: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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