Texas Instruments LP8754EVM, User Manual, Page: 12 / 19

LP8754
C
IN2
C
IN1
C
IN4
C
IN3
C
O
U
T
4
C
O
U
T
3
C
O
U
T
1
C
O
U
T
2
C
IN
5
L2 L1 L0
L5 L4 L3
C
V
D
D
A
C
V
L
D
O
C
VIOSYS
7.5 mm
11 mm
C
IN
6
C
O
U
T
6
C
O
U
T
5
Board Layout
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Figure 5. Component placement near the LP8754. Capacitors marked with X are optional.
Figure 6. Top-layer. Input capacitors are placed close to
Figure 7. 2nd Layer (GND). GND plane kept intact under
the LP8754 and routed on top layer. GND nets are
the high current traces to provide shortest possible return
connected to the GND plane (2nd layer) with microvias.
path for high frequencies.
VIN nets are connected to the VIN plane (3rd layer) with
vias in pads of the input capacitors. VOUT pads of the
output capacitors and inductors are connected together
with large copper area.
12 The LP8754 Evaluation Module SNVU369 – August 2014
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