manualshive.com logo in svg

Texas Instruments LMK5B33216EVM, User Manual, Page: 43 / 53

Share
Download
Texas Instruments LMK5B33216EVM User Manual Download Page 43

6.6 Using the Validation Page

The Validation page allows the user to enable/disable different detectors for reference validation along with 
DPLL frequency and phase lock requirements. Press the 

Reassign All

 button at the top of the page to 

recalculate the validation values.

Figure 6-19. Validation Page

6.7 Using the GPIO Page

The GPIO page allows users to configure the GPIO0, GPIO1, and GPIO2 pins.

When using SPI readback on the EVM, GPIO2 must be configured as 

STATUS or INT…

 and 

SDO output

. When 

using the device in I

2

C mode, refer to 

Section 3.3

.

Figure 6-20. GPIO Page

www.ti.com

Appendix A - TICS Pro LMK5B33216 Software

SNAU263A – FEBRUARY 2022 – REVISED JULY 2022

Submit Document Feedback

LMK5B33216EVM User's Guide

43

Copyright © 2022 Texas Instruments Incorporated

Summary of Contents for LMK5B33216EVM

Page 1: ...d Input Reference Inputs IN0 to IN1 Schematic 17 4 5 Clock Outputs OUT0 to OUT3 Schematic 18 4 6 Clock Outputs OUT4 to OUT9 Schematic 19 4 7 Clock Outputs OUT10 to OUT15 Schematic 20 4 8 XO Schematic 21 4 9 Logic I O Interfaces Schematic 22 4 10 USB2ANY Schematic 23 5 EVM Bill of Materials 24 5 1 Loop Filter and Vibration Nonsensitive Capacitors 31 6 Appendix A TICS Pro LMK5B33216 Software 32 6 1 ...

Page 2: ...ee running locked or holdover mode of operation The EVM can be configured through the onboard USB microcontroller MCU interface using a PC with TI s TICS Pro software graphical user interface GUI TICS Pro can be used to program the LMK5B33216 registers Features LMK5B33216 What is Included LMK5B33216EVM 3 ft mini USB cable MPN 3021003 03 What is Needed Windows PC with TICS Pro Software GUI Test Equ...

Page 3: ..._N IN1_P IN0_N IN0_P OUT10_P OUT10_N OUT11_N OUT11_P OUT12_P OUT12_N OUT13_N OUT13_P OUT0_P OUT0_N OUT1_N OUT1_P OUT7_P OUT7_N OUT6_N OUT6_P OUT4_P OUT4_N OUT5_N OUT5_P OUT3_P OUT3_N OUT2_N OUT2_P VIN1 VIN2 Figure 1 1 LMK5B33216EVM Default Setting of Jumpers and DIP Switches www ti com Introduction SNAU263A FEBRUARY 2022 REVISED JULY 2022 Submit Document Feedback LMK5B33216EVM User s Guide 3 Copyr...

Page 4: ...N0_P N and or b 25 MHz reference clock to IN1_P N 4 Connect the USB cable to the USB port at J41 Software Setup 1 If not already installed install TICS Pro software from TI website TICS Pro Software 2 If the MATLAB R2015b 9 0 64 bit runtime is not already installed download and install from MathWorks website While optional for programming and evaluating the default profile settings the Matlab Runt...

Page 5: ...Ctrl L 3 Check the current consumption maximum 1 3 A 4 Check LMK5B33216 Status as shown in Figure 2 2 a Go to the Status page of the GUI b Click Read Status Bits c Make sure to clear the latched bits To clear latched bits i Press the Clear Latched Bits button ii Select Read Status Bits d Wait to confirm the change It may take some time for the DPLL status bits to reflect lock Figure 2 2 Read Statu...

Page 6: ...d holdover stability and allow narrower DPLL loop bandwidths to be used in comparison to the external XO input B J8 SMA connector for external XO To use the external XO remove the jumper from JP4 4 J4 5 J6 7 SMA Ports for Clock Inputs IN0_P N and IN1_P N IN0_N is not populated and IN0_P is configured for single ended input IN1 is configured for differential input 5 J9 11 J10 12 J13 15 J14 16 J17 1...

Page 7: ...0_P OUT0_N OUT1_N OUT1_P OUT7_P OUT7_N OUT6_N OUT6_P OUT4_P OUT4_N OUT5_N OUT5_P OUT3_P OUT3_N OUT2_N OUT2_P VIN1 VIN2 5 5 5 4 2 9 1 6 8 3B 7 3A Figure 3 1 Key Components EVM Top Side www ti com EVM Configuration SNAU263A FEBRUARY 2022 REVISED JULY 2022 Submit Document Feedback LMK5B33216EVM User s Guide 7 Copyright 2022 Texas Instruments Incorporated ...

Page 8: ...DDO and XO In the direct power configuration mode an external 3 3 V supply is provided to VIN1 to power the VDD pins an external 3 3 V supply is provided to VIN2 to power the VDDO pins and an external 3 3 V supply is provided to VIN3 to power the onboard XO Note Not every power connection is used or required to operate the EVM Other power configurations are possible See the power schematics in Fig...

Page 9: ...jacent to designator to select external VIN2 to VDDO Plane JP4 XO Tie pins 1 2 opposite to designator to select 3 3 V from DCDC1 to XO supply Tie pins 3 4 middle pins to select 3 3 V from LDO3 to XO supply Tie pins 5 6 adjacent to designator to select external VIN3 to XO supply 3 2 Logic Inputs and Outputs The logic I O pins of the LMK5B33216 support different functions depending on the device sta...

Page 10: ...Figure 3 4 SPI Mode Jumper Configuration In SPI mode GPIO2 must also be configured as STATUS or INT SPI Readback Data SDO Active High and CMOS to support SPI readback Figure 3 5 GPIO2 Setting for SPI Mode Communication protocols must be set in TICS Pro From the menu bar select USB communications Interface to get the Communication Setup window and change the protocol Figure 3 6 Communication Setup ...

Page 11: ...ncy accuracy and stability in free run or holdover modes For synchronization applications like SyncE or IEEE 1588 the XO input would typically be driven by a low frequency TCXO or OCXO that conforms to the frequency accuracy and holdover stability requirements of the application For proper DPLL operation the XO frequency must have a non integer frequency relationship with the VCO output frequency ...

Page 12: ...itional XO input options use one at a time C70 allows an external reference to be provided at SMA connector XO J8 C71 allows one of the onboard XO TCXO OCXO footprints to be used By default Y1 is populated with a 48 MHz TCXO and selected with the populated R43 and R206 R43 provides the output clock of Y1 to the XO pin of the LMK5B33414 and R206 provides power to Y1 Additional PCB footprints are av...

Page 13: ...e 50 Ω to GND followed by an AC coupling capacitor for HCSL evaluation purposes OUT4 to OUT15 are AC coupled to the SMA ports for LVDS and HSDS evaluation purposes WARNING DC coupled clocks should not be directly connected to RF equipment which cannot accept DC voltage greater than 0 V For example spectrum analyzers and phase noise analyzers 3 8 Status Outputs and LEDS Status outputs signals can b...

Page 14: ...uts were configured as HSDS outputs following the methods described in Section 3 9 Figure 3 12 APLL3 312 5 MHz Phase Noise Performance Figure 3 13 APLL3 156 25 MHz Phase Noise Performance Figure 3 14 APLL3 125 MHz Phase Noise Performance Figure 3 15 APLL3 100 MHz Phase Noise Performance EVM Configuration www ti com 14 LMK5B33216EVM User s Guide SNAU263A FEBRUARY 2022 REVISED JULY 2022 Submit Docum...

Page 15: ...SN1 0402 25V 2200pF C514 GND 0402 25V 2200pF C504 TP501 VDD_XO_DCDC DNP 10V 10uF C515 GND GND 1 2 L503 BLE18PS080SN1 0402 25V 2200pF C516 35V 47uF C500 10uF C23 23 2k R8 13 3k R9 1 A LDO REG LDO3 for XO rail 10uF C22 LDO3 OUT 3 3V IN 1 IN 2 IN CP 3 CP 4 EN 5 GND CP 6 GND 7 FB 8 SET 9 OUT FB 10 OUT 11 OUT 12 DAP 13 LP38798SD ADJ NOPB U9 10nF C24 LDO3_IN LDO3 47k R203 0 01uF C156 GND 1 2 3 4 5 J500 ...

Page 16: ... 10uF C59 0 1uF C58 0 1uF C55 10uF C56 FB10 TP8 VDD_IN0 DNP TP10 VDD_IN1 DNP TP12 VDD_DIG DNP TP14 VDD_APLL1_XO DNP TP16 VDD_APLL2 DNP TP18 VDD_APLL3 DNP VDD_PLANE VDDO_PLANE VCC_XO TP9 VDDO_01 DNP TP11 VDDO_23 DNP TP13 VDDO_4TO7 DNP TP15 VDDO_8TO13 DNP VDDO_1415 0 1uF C42 0 1uF C48 0 1uF C54 0 1uF C60 0 1uF C30 0 1uF C36 0 1uF C33 0 1uF C39 0 1uF C57 0 1uF C45 0 1uF C51 NT1 NT_0603 0 R11 0 R16 0 ...

Page 17: ...L3 48 GPIO0 50 GPIO1 64 GPIO2 10 CAP1_APLL2 22 CAP2_APLL2 21 CAP3_APLL2 20 CAP_DIG 40 IN0_N 35 IN0_P 34 IN1_N 38 IN1_P 39 U1 EXT SMA XO CLK SMA_XO_P XO2_P 0 R41 1 2 3 4 5 J8 142 0701 201 49 9 R42 DNP XO1_P 0 1uF R40 0 1uF C70 0 1uF C71 25V 100nF C67 25V 0 047µF C68 DNP SMA_IN0_P SMA_IN0_N 0 R30 0 R26 0 R31 0 R27 51 R32 51 R28 DNP R_IN0_P R_IN0_N 100 R29 DNP IN0_N IN0_P SMA_IN1_P SMA_IN1_N 0 R37 0 ...

Page 18: ... ClassName OUT_LenMatch1a ClassName OUT_LenMatch1a ClassName OUT_LenMatch1a ClassName OUT_LenMatch1a ClassName OUT_LenMatch1a ClassName OUT_LenMatch1a ClassName OUT_LenMatch1b ClassName OUT_LenMatch1b ClassName OUT_LenMatch1b ClassName OUT_LenMatch1b ClassName OUT_LenMatch1b ClassName OUT_LenMatch1b ClassName OUT_LenMatch1b ClassName OUT_LenMatch1b 0 R6 0 R10 0 R81 0 R84 0 R7 0 R80 0 R83 0 R87 49 ...

Page 19: ...e may be VCO2 or VCO3 OUT9 Supported formats LVDS HSDS and HCSL Source may be VCO2 or VCO3 SMA_O4_P SMA_O4_N ClassName OUT_LenMatch2a ClassName OUT_LenMatch2a ClassName OUT_LenMatch2a ClassName OUT_LenMatch2a ClassName OUT_LenMatch1a ClassName OUT_LenMatch1a ClassName OUT_LenMatch2b ClassName OUT_LenMatch2b ClassName OUT_LenMatch2a ClassName OUT_LenMatch2b ClassName OUT_LenMatch2a ClassName OUT_Le...

Page 20: ...LenMatch1a ClassName OUT_LenMatch1a ClassName OUT_LenMatch1a ClassName OUT_LenMatch1a ClassName OUT_LenMatch1a ClassName OUT_LenMatch1a ClassName OUT_LenMatch2a ClassName OUT_LenMatch2b ClassName OUT_LenMatch2a ClassName OUT_LenMatch2b ClassName OUT_LenMatch2a ClassName OUT_LenMatch2b ClassName OUT_LenMatch2a ClassName OUT_LenMatch2b ClassName OUT_LenMatch1b ClassName OUT_LenMatch1b ClassName OUT_...

Page 21: ... GND 7 Y5 ROX2522S4 DNP VCC_XO_FILT EN_XO EN_XO VCC_XO_FILT VCC_XO_FILT VCC_XO_FILT 33 R49 DNP XO3 33 R47 DNP XO3 33 R48 DNP XO3 33 R46 DNP XO3 TP30 Vc DNP 100pF C86 DNP OE 1 NC 2 GND 3 CLK 4 CLK 5 VDD 6 CDC64XX 2520 U4 DNP 33 R50 DNP XO3 VCC_XO_FILT EN_XO 0 1uF C82 0 1uF C83 DNP 0 1uF C85 DNP 0 1uF C87 DNP 0 1uF C84 DNP ClassName XO_trace ClassName XO_trace ClassName XO_trace ClassName XO_trace C...

Page 22: ...73 6 3 1 8 2 7 5 4 S4 SW_4SPST Active High LED 2 5 mA LMKGPIO2 U2AGPIO5 SOMI 1 5k R58 1 5k R57 U2A_3V3 SH5 1 5k R60 DNP 1 5k R59 DNP U2A_3V3 U2AGPIO6 U2AGPIO2 U2AGPIO0 U2AGPIO1 U2AGPIO4 U2AGPIO5 U2AGPIO8 U2AGPIO5 SOMI U2AGPIO3 U2AGPIO7 SH6 Red 1 2 D6 SCLK BUSY 470 R54 0 R61 1 2 4 U5A U2A_I2CPU SCLK 1 3 D8 DIODE_BAT54 0 01uF C90 100k R62 VDD_PLANE VDDGPIO 0 1uF C89 3 1 2 Q2 FDV301N GND 3 VCC 5 U5B ...

Page 23: ...M_UCA1STE 48 DVSS2 49 DVCC2 50 P4 4 PM_UCA1TXD PM_UCA1SIMO 51 P4 5 PM_UCA1RXD PM_UCA1SOMI 52 P4 6 PM_NONE 53 P4 7 PM_NONE 54 P5 6 TB0 0 55 P5 7 TB0 1 56 P7 4 TB0 2 57 P7 5 TB0 3 58 P7 6 TB0 4 59 P7 7 TB0CLK MCLK 60 VSSU 61 PU 0 DP 62 PUR 63 PU 1 DM 64 VBUS 65 VUSB 66 V18 67 AVSS2 68 P5 2 XT2IN 69 P5 3 XT2OUT 70 TEST SBWTCK 71 PJ 0 TDO 72 PJ 1 TDI TCLK 73 PJ 2 TMS 74 PJ 3 TCK 75 RST NMI SBWTDIO 76 ...

Page 24: ...F 10 V 10 X5R 0402 C1005X5R1A104K050BA TDK C61 1 0 1uF CAP CERM 0 1 uF 50 V 10 X7R 0603 C1608X7R1H104K080AA TDK C75 C141 2 0 47uF CAP CERM 0 47 uF 10 V 10 X7R 0603 GRM188R71A474KA61D MuRata C89 C132 C133 C137 C138 C142 C143 C144 8 0 1uF CAP CERM 0 1 uF 16 V 5 X7R 0603 C0603C104J4RACTU Kemet C90 C154 C155 C156 4 0 01uF CAP CERM 0 01 uF 50 V 5 X7R 0603 C0603C103J5RACTU Kemet C98 C100 C101 C102 C103 ...

Page 25: ... Diode Schottky 20 V 2 A SMA B220A 13 F Diodes Inc D3 D4 D5 D12 4 Green LED Green SMD LTST C190GKT Lite On D6 1 Red LED Red SMD LTST C170KRKT Lite On D7 D9 D10 3 Yellow LED Yellow SMD LTST C170KSKT Lite On D8 1 30V Diode Schottky 30 V 0 2 A SOT 23 BAT54 7 F Diodes Inc FB1 FB2 FB3 FB4 FB5 FB6 FB7 FB8 FB9 FB10 FB11 11 220 ohm Ferrite Bead 220 ohm 100 MHz 2 5 A 0603 BLM18SG221TN1D MuRata FB12 1 300 o...

Page 26: ... 200 H 10 000 per roll THT 14 423 10 Brady Q1 Q3 Q4 Q5 4 50V MOSFET N CH 50 V 0 22 A SOT 23 BSS138 Fairchild Semiconductor Q2 1 25V MOSFET N CH 25 V 0 22 A SOT 23 FDV301N Fairchild Semiconductor R1 R3 R8 3 23 2k RES 23 2 k 1 0 1 W AEC Q200 Grade 0 0603 CRCW060323K2FKEA Vishay Dale R2 R5 R9 3 13 3k RES 13 3 k 1 0 1 W AEC Q200 Grade 0 0603 CRCW060313K3FKEA Vishay Dale R6 R7 R10 R80 R81 R83 R84 R87 R...

Page 27: ... 25 W AEC Q200 Grade 0 0603 ESR03EZPJ101 Rohm R145 R148 R165 3 33k RES 33 k 5 0 1 W AEC Q200 Grade 0 0603 CRCW060333K0JNEA Vishay Dale R147 1 1 5k RES 1 5 k 5 0 063 W AEC Q200 Grade 0 0402 CRCW04021K50JNED Vishay Dale R149 1 1 2Meg RES 1 2 M 5 0 1 W AEC Q200 Grade 0 0603 CRCW06031M20JNEA Vishay Dale R161 R162 R166 3 510 RES 510 5 0 1 W AEC Q200 Grade 0 0603 CRCW0603510RJNEA Vishay Dale R168 R170 R...

Page 28: ...06A USON 6 TPD4E004DRYR Texas Instruments U8 1 25 MHz Mixed Signal Microcontroller with 128 KB Flash 8192 B SRAM and 63 GPIOs 40 to 85 degC 80 pin QFP PN Green RoHS no Sb Br MSP430F5529IPN Texas Instruments U9 U10 U11 3 800 mA Ultra Low Noise High PSRR LDO DNT0012B WSON 12 LP38798SD ADJ NOPB Texas Instruments U500 1 3A Low Noise and Low Ripple buck converter RPU0010A VQFN 10 TPS62913RPUT Texas Ins...

Page 29: ... 0 33 RES 33 5 0 063 W AEC Q200 Grade 0 0402 CRCW040233R0JNED Vishay Dale R59 R60 0 1 5k RES 1 5 k 5 0 1 W AEC Q200 Grade 0 0603 CRCW06031K50JNEA Vishay Dale R78 R79 R82 R85 R86 R88 R90 R92 R94 R96 R99 R101 R103 R105 R109 R111 R113 R115 R117 R119 R121 R122 R125 R127 R129 R131 R133 R134 R135 R136 R137 R138 R139 R140 R141 R142 R143 R167 R169 R175 R176 R177 R178 R179 R180 R181 R182 R183 R184 R185 R18...

Page 30: ... 8W48072003 TXC Corporation Y3 0 Crystal Sealed Locked 50 MHz 15pF SMD 7X 50 000MBB T TXC Corporation Y4 0 MERCURY 38 88MHz OCXO CMOS Oscillator 2 7 5V 4 SMD ROM9070PA Rakon Y5 0 STANDARD OCXO 10MHz Frequency ROX2522S4 Rakon EVM Bill of Materials www ti com 30 LMK5B33216EVM User s Guide SNAU263A FEBRUARY 2022 REVISED JULY 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 31: ...or vibration immune loop filter components Table 5 2 Examples of Substitute Capacitors Which are Vibration Immune CAPACITOR VALUE VIBRATION SENSITIVE X7R VIBRATION IMMUNE 3 3 nF C0603C332K5RACTU 0603 GRM1885C1H332JA01D C0G NP0 0603 33 nF C0603C333J3RACTU 0603 C2012C0G1H333J125AA C0G NP0 0805 47 nF 06035C473JAT2A 0603 C0805X473G3GEC7800 C0G NP0 0805 C0805C473J3GACTU C0G NP0 0805 0 1 µF C0603C104J3R...

Page 32: ...ence to each PLL and associated settings for PLL phase detector frequency 6 1 2 Step 2 In Step 2 set up the clock input frequencies and the interface type Cascaded APLLs can also be assigned from this page using the PLL R divider and phase detector preview to the right Figure 6 2 Step 1 and 2 XO Input and Clock Inputs Appendix A TICS Pro LMK5B33216 Software www ti com 32 LMK5B33216EVM User s Guide...

Page 33: ...frequencies The corresponding APLL is listed next to the REF4 and REF5 The REF with the highest priority will be fed as the DPLL input Figure 6 3 Step 3 DPLL Clock Input Selection 6 1 4 Step 4 Set the clock output for ZDM The PLL will drive the PLL source mux for the selected output set for ZDM Figure 6 4 Step 4 Zero Delay Mode www ti com Appendix A TICS Pro LMK5B33216 Software SNAU263A FEBRUARY 2...

Page 34: ...ecting the Enable User Override checkbox and typing in the desired VCO frequencies The Copy to Selected VCO Frequency box can also be used to copy the VCO frequency in the list selections to the VCO overrides Press the Assign Selected VCO Settings to Device button to update the VCO frequencies then press the Apply Output Clock Settings to Device button By default the analog PLL frequencies are sho...

Page 35: ... the Status Page The Status page shows fields pertaining to the current status of the device To update these fields click the Read Status Bits button or the Read RO Regs button in the toolbar The Read RO Regs button will read all read only registers which provides more information on other pages including the status fields but can take longer to read back The read status bits just reads the status...

Page 36: ... that the DPLL frequency is the exact desired frequency Each DPLL supports two sets of DPLL dividers which can be selected At this time the tool calculates the divider for FB Config 1 only To use two different feedback dividers the following procedure should be preformed 1 Div 1 settings may be copied into Div 2 settings and selected for use by the DPLL Div Select control 2 The references that req...

Page 37: ...e within 5 for the two DPLL feedback configurations Figure 6 9 APLL or DPLL Frequency Selection Figure 6 10 PLL3 Input www ti com Appendix A TICS Pro LMK5B33216 Software SNAU263A FEBRUARY 2022 REVISED JULY 2022 Submit Document Feedback LMK5B33216EVM User s Guide 37 Copyright 2022 Texas Instruments Incorporated ...

Page 38: ...p simultaneously Figure 6 11 Cascade APLL Start Priorities 6 3 1 1 Cascade VCO to APLL Reference Cascading APLLs is controlled by the APLL source box shown in Figure 6 12 This box is programmed bitwise and is automatically set when generating a frequency plan The XO_OUT_BUF_EN register in the Input Control section of the User Controls tab is automatically set to enable or disable the XO Output Buf...

Page 39: ...ered step size will be used to calculate a numerator deviation and a 2s complement numerator deviation To perform the shift the increment or decrement button must be pressed An increment will write the numerator deviation to the DPLLx_FREE_RUN control which will result in a positive frequency shift in the amount specified by the DCO Step Size ppb An decrement will write the 2s complement numerator...

Page 40: ...ximum value A value of 63 will result in the fastest adjustment Figure 6 16 APLL DCO Controls 6 5 Using the DPLL1 DPLL2 and DPLL3 Pages The DPLL pages contain many advanced controls that are normally set during the Run Script calculation Appendix A TICS Pro LMK5B33216 Software www ti com 40 LMK5B33216EVM User s Guide SNAU263A FEBRUARY 2022 REVISED JULY 2022 Submit Document Feedback Copyright 2022 ...

Page 41: ...Primary DPLL Controls www ti com Appendix A TICS Pro LMK5B33216 Software SNAU263A FEBRUARY 2022 REVISED JULY 2022 Submit Document Feedback LMK5B33216EVM User s Guide 41 Copyright 2022 Texas Instruments Incorporated ...

Page 42: ...ion that will be applied to the DPLL numerator This frequency deviation is shown in the DPLLx_FDEV control To perform the shift the increment or decrement button must be pressed Figure 6 18 DPLL DCO Controls Appendix A TICS Pro LMK5B33216 Software www ti com 42 LMK5B33216EVM User s Guide SNAU263A FEBRUARY 2022 REVISED JULY 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated...

Page 43: ...e 6 19 Validation Page 6 7 Using the GPIO Page The GPIO page allows users to configure the GPIO0 GPIO1 and GPIO2 pins When using SPI readback on the EVM GPIO2 must be configured as STATUS or INT and SDO output When using the device in I2C mode refer to Section 3 3 Figure 6 20 GPIO Page www ti com Appendix A TICS Pro LMK5B33216 Software SNAU263A FEBRUARY 2022 REVISED JULY 2022 Submit Document Feedb...

Page 44: ...ming OUT_x_y_SR_GPIO_EN 1 and GPIO_SYSREF_SEL to the appropriate OUT_x_y The GPIOx replicated SYSREF output will be a continuous frequency Pulsed SYSREF mode is not supported for the GPIOx replica outputs Figure 6 21 SYNC SYSREF 1 PPS Page 6 8 Using the Outputs Page The Outputs page shows all the possible source frequencies to the output channels To simplify settings fields necessary to providing ...

Page 45: ... signifies that all these outputs should source from the same VCO Figure 6 22 Outputs Page www ti com Appendix A TICS Pro LMK5B33216 Software SNAU263A FEBRUARY 2022 REVISED JULY 2022 Submit Document Feedback LMK5B33216EVM User s Guide 45 Copyright 2022 Texas Instruments Incorporated ...

Page 46: ...o the device EEPROM To program the EEPROM press the Program EEPROM button Figure 6 23 EEPROM Page Appendix A TICS Pro LMK5B33216 Software www ti com 46 LMK5B33216EVM User s Guide SNAU263A FEBRUARY 2022 REVISED JULY 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 47: ...he EVM image schematic images BOM table and Power Supply section 8 Added Additional XO Input Options section 12 Changed TICS Pro GUI images to the latest LMK5B33216 TICS Pro profile 32 Changed APLL DCO page description 42 Changed SYNC SYSREF 1 PPS page description 44 Changed EEPROM page description 46 Changed Design Report page description 47 www ti com Appendix A TICS Pro LMK5B33216 Software SNAU...

Page 48: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 49: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 50: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 51: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 52: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 53: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

Reviews:

No comments