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11.10 Other Page

The

Other

page contains some registers to control the GPIO pins of the LMK04832. Each pin has two fields, the

first is the _TYPE field which allows the input or output mode of the pin to be defined. The second is the _MUX
field which, when set for output, controls what the pin will output.

Figure 11-10. TICS Pro - Other Page

TICS Pro Usage

34

LMK04368EPEVM User’s Guide

SNAU283 – OCTOBER 2022

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Copyright © 2022 Texas Instruments Incorporated

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Summary of Contents for LMK04368EPEVM

Page 1: ... TICS Pro Application 5 5 2 Select Device 5 5 3 Program the Device 6 5 4 Restoring a Default Mode 6 5 5 Visual Confirmation of Frequency Lock 7 5 6 Enable Clock Outputs 7 6 Evaluation Board Inputs and Outputs 9 7 Recommended Test Equipment 12 8 Schematics 13 9 Bill of Materials 16 A USB2ANY Firmware Upgrade 21 B TICS Pro Usage 25 11 1 Communication Setup 25 11 2 User Controls 26 11 3 Raw Registers...

Page 2: ...P EVM allows full verification of the device functionality and performance specifications To quickly set up and operate the board with basic equipment refer to the quick start procedure below and test setup shown in Figure 2 1 1 Connect a voltage of 4 5 V to the VCC SMA connector or terminal block The LMK04368 EP and onboard VCXO operate at 3 3 V provided by the onboard TPS7A4701 EP LDO and LP5900...

Page 3: ... 25 24 26 27 18 3 10 Figure 2 2 Clock Outputs Page Description Diagram 1 SYNC_DISX Prevent the divider from being reset by SYNC SYSREF path 2 DCLKX_Y_DIV Divide value for the device clock If set to 1 then DCLKX_Y_DCC DCC HS must 1 3 DDLYdX_EN Enable dynamic digital delay for this divider 4 DCLKX_Y_HSg_PD If clear glitchless half step adjustments are enabled 5 DCLKX_Y_HS Set half step for this divi...

Page 4: ...e the impact of the reference clock phase noise The reference clock consequently serves only as a frequency reference rather than a phase reference The loop filters on the LMK04368EPEVM evaluation board are set up using the approach above The loop filter for PLL1 has been configured for a narrow loop bandwidth 1 kHz The specific loop bandwidth values depend on the phase noise performance of the os...

Page 5: ...8 MHz Figure 4 1 Selecting a Default Mode for the LMK04368 EP Device 5 Using TICS Pro to Program the LMK04368 EP This section will demonstrate how to use TICS Pro For more information on using TICS Pro refer to Appendix A TICS Pro is available for download at http www ti com tool ticspro sw Before proceeding be sure to follow the instructions in Section 2 to ensure proper hardware connections 5 1 ...

Page 6: ...ensuring there is no checkmark by the Options AutoUpdate A default mode will be restored in the next step therefore this step is not necessary It is included however to emphasize the importance of pressing Ctrl L to load the device at least once after starting TICS Pro restoring a mode or restoring a saved setup using the File menu See TICS Pro instructions located at http www ti com tool ticspro ...

Page 7: ... If Clock Divider 1 then DCLKX_Y_DCC must be set for clock output iii Phase of the device clock can be adjusted with 1 Static Digital delay DCLKX_Y_DDLY after a SYNC Digital Delay DCLKX_Y_DDLY_PD must be powered up 2 Dynamic Digital delay DDLYdX_EN then programming DDLYd_STEP_CNT Digital Delay DCLKX_Y_DDLY_PD must be powered up Press the Send button at top right of Clock Outputs window to program ...

Page 8: ...e instrument c For HSDS i A balun like ADT2 1T or high quality Prodyn BIB 100G is recommended for differential to single ended conversion d For CML i A balun can be used or ii One side of the CML signal can be terminated with a 50 Ω load and the other side can be run single ended to the instrument e For LVCMOS i Connect the LVCMOS signal to measurement equipment as desired If an output of a pair i...

Page 9: ...1 9 through the CLKoutX_FMT control All clock outputs are AC coupled to allow safe testing with RF test equipment If an output pair is programmed to LVCMOS each output can be independently configured normal inverted or off tri state Best performance EMI reduction is achieved by using a complementary output mode like Norm Inv TI does NOT recommend using Norm Norm or Inv Inv mode Not Populated CLKou...

Page 10: ... Clock Distribution with Fin0 or CLKin1 Fin1 Fin0 and CLKin1 Fin1 are shared for use as an RF Input for Clock Distribution mode or for an external VCO mode External Feedback Input FBCLKin for 0 Delay CLKin1 is shared for use as an external feedback clock input FBCLKin to PLL1 N or PLL2 N for 0 delay mode Refer to the LMK04368 EP data sheet for more details on using 0 delay mode with the evaluation...

Page 11: ...C SYNC TP10 J46 CMOS Input Output Programmable status I O pin By default set as an input pin for synchronize the clock outputs with a fixed and known phase relationship between each clock output selected for SYNC A SYNC event also causes the digital delay values to take effect SYNC SYSREF_REQ pin forces the SYSREF_MUX into SYSREF Continuous mode 0x03 when SYSREF_REQ_EN 1 SYNC SYSREF_REQ pin can ho...

Page 12: ... output clocks AC performance such as rise time or fall time propagation delay or skew TI suggests using a real time oscilloscope with 8 GHz analog input bandwidth with 50 Ω inputs To evaluate clock synchronization or phase alignment between multiple clock outputs TI recommends using phase matched 50 Ω cables to minimize external sources of skew or other errors distortion that may be introduced if...

Page 13: ...nd on the following schematic by searching for their reference designators Figure 8 1 Schematic LMK04368 EP www ti com Schematics SNAU283 OCTOBER 2022 Submit Document Feedback LMK04368EPEVM User s Guide 13 Copyright 2022 Texas Instruments Incorporated ...

Page 14: ...gure 8 2 Schematic Power Supply Figure 8 3 Schematic Digital Schematics www ti com 14 LMK04368EPEVM User s Guide SNAU283 OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 15: ...hematic Clock Outputs 1 of 2 Figure 8 5 Schematic Clock Outputs 2 of 2 www ti com Schematics SNAU283 OCTOBER 2022 Submit Document Feedback LMK04368EPEVM User s Guide 15 Copyright 2022 Texas Instruments Incorporated ...

Page 16: ...X7R 0603 1608 Metric CC0603KRX7R6BB684 0603 Yageo C15 CAP CERM 0 1 uF 16 V 10 X7R 0603 C0603C104K4RACTU 0603 Kemet C16 C19 C27 C29 C32 C36 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 CAP CERM 0 1 µF 10 V 10 X7R 0402 C0402C104K8RACTU 0402 Kemet C21 CAP CERM 100 pF 50 V 5 C0G NP0 0603 C0603C101J5GACTU 0603 Kemet C24 C28 CAP ...

Page 17: ...M155R71E103KA37D 0402 MuRata C95 CAP CERM 0 1 uF 25 V 10 X7R 0603 C0603C104K3RACTU 0603 Kemet C105 C111 C115 C118 CAP CERM 0 1 uF 25 V 10 X7R 0402 GRM155R71E104KE14D 0402 MuRata C107 CAP CERM 0 01 uF 50 V 5 X7R 0603 C0603C103J5RACTU 0603 Kemet C123 C126 C129 C134 C137 CAP CERM 1 uF 10 V 10 X7S AEC Q200 Grade 1 0402 GCM155C71A105KE38D 0402 MuRata D1 D2 LED Green SMD 150141VS73100 2 8x1 9x3 2mm Wurt...

Page 18: ... 0 22 A SOT 23 BSS138 SOT 23 Fairchild Semiconductor R1 R3 R4 R6 R12 R25 R33 R34 R46 R47 R62 R68 R109 R112 R114 R116 R133 R137 R140 R150 R163 R169 R193 R202 RES 0 5 0 063 W AEC Q200 Grade 0 0402 CRCW04020000Z0ED 0402 Vishay Dale R5 R15 R23 R26 RES 18 5 0 063 W 0402 CRCW040218R0JNED 0402 Vishay Dale R8 R11 R48 R53 RES 10 5 0 1 W AEC Q200 Grade 0 0603 CRCW060310R0JNEA 0603 Vishay Dale R9 RES 100 1 0...

Page 19: ... Dale R74 RES 51 k 5 0 1 W AEC Q200 Grade 0 0603 CRCW060351K0JNEA 0603 Vishay Dale R81 RES 330 5 0 1 W 0603 CRCW0603330RJNEA 0603 Vishay Dale R84 RES 10 k 5 0 1 W 0603 CRCW060310K0JNEA 0603 Vishay Dale R86 RES 33 k 5 0 1 W AEC Q200 Grade 0 0603 CRCW060333K0JNEA 0603 Vishay Dale R90 RES 1 5 k 5 0 1 W AEC Q200 Grade 0 0603 CRCW06031K50JNEA 0603 Vishay Dale R92 RES 1 2 M 5 0 1 W AEC Q200 Grade 0 0603...

Page 20: ...s U3 4 Channel ESD Protection Array for High Speed Data Interfaces DRY0006A USON 6 TPD4E004DRYR DRY0006A Texas Instruments U4 Ultra Low Noise 150mA Linear Regulator for RF Analog Circuits Requires No Bypass Capacitor 6 pin LLP Pb Free LP5900SDX 3 3 NOPB NGF0006A Texas Instruments U5 150 mA Ultra Low Noise LDO for RF and Analog Circuits Requires No Bypass Capacitor NGF0006A WSON 6 LP5900SD 3 3 NOPB...

Page 21: ...to complete the update 1 When the USB2ANY Firmware Requirement pop up window appears click OK to continue Figure A 1 Firmware Requirement 2 The Firmware Loader pop up window will load Disconnect the USB cable from the EVM Figure A 2 Firmware Loader 3 Press and hold the BSL button while you connect the USB2ANY cable www ti com USB2ANY Firmware Upgrade SNAU283 OCTOBER 2022 Submit Document Feedback L...

Page 22: ...Figure A 3 BSL Button Location USB2ANY Firmware Upgrade www ti com 22 LMK04368EPEVM User s Guide SNAU283 OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 23: ...ear Figure A 4 Update Firmware 5 Click Upgrade Firmware to start the firmware upgrade Click Close after the upgrade is complete Figure A 5 Firmware Update Complete www ti com USB2ANY Firmware Upgrade SNAU283 OCTOBER 2022 Submit Document Feedback LMK04368EPEVM User s Guide 23 Copyright 2022 Texas Instruments Incorporated ...

Page 24: ...e to check the USB connection Make sure the USB Connected button is green Figure A 6 USB Communications USB2ANY Firmware Upgrade www ti com 24 LMK04368EPEVM User s Guide SNAU283 OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 25: ...tion Setup window allows you to select the USB2ANY or DemoMode interface In case you plan to connect multiple evaluation boards to your PC and run multiple instances of the TICS Pro software the drop down box will allow you to select specific USB2ANY devices Press the Identify button to determine which USB2ANY is currently selected Devices used by other instances of TICS Pro will not display in th...

Page 26: ...rols typically not included on one of the other dedicated pages Figure 11 2 TICS Pro User Controls Page TICS Pro Usage www ti com 26 LMK04368EPEVM User s Guide SNAU283 OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 27: ...the list of registers and displayed in the top right An individual register or field may be read back by entering the name into the bottom right and clicking the Read button Register maps may be exported but also imported The import format may simply be the address and register data in hex format as illustrated in the address value column one register to a line Note Use the Export Register Map opt...

Page 28: ...allows the user to set high level usage profiles to allow the device to operate in dual loop single loop or distribution mode The bottom LMK04832 sub modes section allows further JESD204B configuration 0 delay configuration or clock input configuration which may apply for many of the LMK04832 modes of operation Figure 11 4 TICS Pro Set Modes Page TICS Pro Usage www ti com 28 LMK04368EPEVM User s G...

Page 29: ...hreshold the input must be above approximately 200 MHz to lock otherwise PLL1 will enter holdover If holdover is not enabled PLL1 will be prevented from locking if the input frequency is less than the threshold frequency and LOS is enabled In addition to the above steps auto clock selection mode must be used to allow the LMK04832 to automatically switch to holdover when enabled clocks for auto swi...

Page 30: ... by which the active CLKinX is selected and change the routing options for the CLKinX inputs You can also reset the PLL1 R or PLL2 N divider on this page Figure 11 6 TICS Pro CLKinX Control Page TICS Pro Usage www ti com 30 LMK04368EPEVM User s Guide SNAU283 OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 31: ...lay red text will help guide the user through properly setting up 0 delay mode When using dual PLL mode the OSCin Source combo box can be set to External VCXO which links the OSCin frequency with the external VCXO frequency When using single PLL2 mode the OSCin Source combo box can be set to Independent to allow the OSCin frequency to be unlinked from the external VCXO frequency Figure 11 7 TICS P...

Page 32: ...e toolbar as SYNC Dividers Note To use SYNC or SYSREF ensure that SYNC_EN 1 To use SYSREF in continuous pulser or reclocked modes be sure SYSREF_PD 0 The SCLKX_Y_DIS_MODE bits allow the clock outputs to be disabled or set to a low state Values 1 and 2 are only conditionally set by the SYSREF_GBL_PD bit therefore it is possible to power up down several SYSREF outputs by programming only one registe...

Page 33: ...wo SYSREF clocks or one of each The naming convention uses X_Y for controls which can impact both CLKoutX even clock and CLKoutY odd clock X for controls impacting only CLKoutX and Y for controls impacting only CLKoutY Figure 11 9 TICS Pro Clock Outputs Page www ti com TICS Pro Usage SNAU283 OCTOBER 2022 Submit Document Feedback LMK04368EPEVM User s Guide 33 Copyright 2022 Texas Instruments Incorp...

Page 34: ...YPE field which allows the input or output mode of the pin to be defined The second is the _MUX field which when set for output controls what the pin will output Figure 11 10 TICS Pro Other Page TICS Pro Usage www ti com 34 LMK04368EPEVM User s Guide SNAU283 OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 35: ...e user to program sequences of register programming or pin control Figure 11 11 TICS Pro Burst Mode Page www ti com TICS Pro Usage SNAU283 OCTOBER 2022 Submit Document Feedback LMK04368EPEVM User s Guide 35 Copyright 2022 Texas Instruments Incorporated ...

Page 36: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 37: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 38: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 39: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 40: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 41: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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