Texas Instruments LMK04208 User Manual Download Page 24 | Manualshive

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Clock Outputs Page

24

SNAU200 – September 2016

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Copyright © 2016, Texas Instruments Incorporated

TICS Pro Usage

A.3

Clock Outputs Page

The

Clock Distribution

page allows the user to control the output channel blocks.

If a 0-delay mode is being used, changing the clock output frequency (divider or source) in the feedback
path may impact PLL lock.

Figure 14. Clock Outputs Page

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Summary of Contents for LMK04208

Page 1: ...LMK04208 User s Guide Literature Number SNAU200 September 2016 ...

Page 2: ...on 8 6 2 Select Device 8 6 3 Setup and Confirm Communications 8 6 4 Restoring a Default Mode 9 6 5 Program Load Device 9 6 6 Visual Confirmation of Frequency Lock 9 6 7 Enable Clock Outputs 10 7 Evaluation Board Inputs and Outputs 11 8 Recommended Test Equipment 14 9 Schematics 15 10 Bill of Materials 20 Appendix A TICS Pro Usage 22 A 1 Communication Setup Window 22 A 2 CLKins and PLLs Page 23 A 3...

Page 3: ...8 User s Guide 1 Introduction This user s guide describes how to set up and operate the LMK04208 evaluation module EVM The LMK04208 is the industry s highest performance clock conditioner with JEDEC JESD204B support 2 Evaluation Board Kit Contents The evaluation board kit includes what is shown in Table 1 Table 1 EVM Contents SV601293 001 Evaluation Board 1 LMK04208 Evaluation Board USB Communicat...

Page 4: ...t0 D4 Holdover_TP Status_Holdover pin 1 Default is LDO to IC Do not connect 4 to 5 V direct to IC typical 3 3 V USB2ANY Programming Connection OSCin OSCin USB2ANY USB Cable 122 88 MHz VCXO CLKin1_IND Place 270 ohm on R46 to connect CLKin0_IND Place 270 ohm on R47 to connect SYNC_TP All CLKout and OSCout outputs are capable of LVDS LVPECL and LVCMOS output formats However the output format suited t...

Page 5: ...SB2ANY is selected Select specific USB2ANY interface to use click Identify to confirm selected USB2ANY and valid communications to USB2ANY by blinking LED If LMK04208EVM or USB2ANY available the software may be run in DemoMode for evaluation and generation of register programming data Press Close to exit Communication Setup c From menu bar click Default configuration to select a default mode For t...

Page 6: ...er controls shows help in the Context window to bottom left of screen In bottom left of screen is displayed a General help for the page After context help has been displayed click this tab to view again To enable read back for LMK04208 a 0 Ω resistor must be placed at R59 this shares Status_Holdover for use as read back R59 is located just below the red D4 Status_Holdover LED ...

Page 7: ...p www ti com tool clockdesigntool 4 1 PLL1 Loop Filter 1 Loop Bandwidth and Phase Margin is a function of Kφ Kvco N as well as loop components Changing Kφ and N by device programming will change the loop bandwidth Table 2 PLL1 Loop Filter Parameters for VCXO with 8 kHz V Tuning Sensitivity 1 PLL1 using 122 88 MHz VCXO Epson VG 4513CA 122 8800M GFCT3 Loop Bandwidth 20 Hz Phase Margin 50 Kφ Charge P...

Page 8: ...208 device will serve as an example For more information on using TICS Pro refer to Appendix A and TICS Pro instructions Help TICS Pro User Manual Before proceeding be sure to follow the instructions in Section 3 to ensure proper connections 6 1 Start TICS Pro Application Click Start Programs Texas Instruments TICS Pro TICS Pro The TICS Pro program is installed by default to the TICS Pro applicati...

Page 9: ... of the newly loaded LMK04208 file Figure 5 Loading the Device Once the device has been initially loaded TICS Pro will automatically program changed registers so it is not necessary to reload the device upon subsequent changes in the device configuration It is possible to disable this functionality by ensuring there is no checkmark by the Options AutoUpdate Because a default mode will be restored ...

Page 10: ... Set the following as needed a Digital Delay value 1 b Clock Divider value 3 c Analog Delay Select and Analog Delay Value if desired 4 and 5 Analog delay will add to noise floor of output Figure 6 Setting Digital Delay Clock Divider Analog Delay and Output Format 4 Depending on the configured output type the clock output SMAs can be interfaced to a test instrument with a single ended 50 Ω input as...

Page 11: ... use Norm Norm or Inv Inv mode Populated OSCout OSCout Analog Output Buffered output of OSCin port The output terminations on the evaluation board are shown below OSC Output Default Board Termination OSCout open LVDS LVCMOS OSCout has a programmable LVDS LVPECL or LVCMOS output buffer The output buffer type can be selected in TICS Pro on the Clock Outputs page via the OSCout_TYPE control OSCout is...

Page 12: ...connectors with minor modification to the components going to the OSCin OSCin pins of device This is useful if the VCXO footprint does not accommodate the desired VCXO device or if the user desires to use the LMK04208 in single loop mode It is also necessary to connect the Vtune input of the VCXO to the CPout1 A single ended or differential signal may be used to drive the OSCin OSCin pins and must...

Page 13: ...By default set as input pins for controlling input clock switching of CLKin0 and CLKin1 if Pin Select mode is enabled by CLKin_Select_MODE These inputs will not be functional because CLKin_SEL_MODE is set to 0 CLKin0 Manual by default in the User Controls page in TICS Pro To enable input clock switching CLKin_SEL_MODE must be 3 and Status_CLKinX_TYPE must be 0 to 2 pin enabled as an input Input Cl...

Page 14: ...rchitecture of the E5052 is superior for phase noise measurements At frequencies less than 100 MHz the local oscillator noise of the E4445A is too high and measurements will reflect the E4445A s internal local oscillator performance not the device under test Oscilloscope To measure the output clocks for AC performance such as rise time or fall time propagation delay or skew it is suggested to use ...

Page 15: ...www ti com Schematics 15 SNAU200 September 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LMK04208 User s Guide 9 Schematics Figure 7 Power Supply ...

Page 16: ...Schematics www ti com 16 SNAU200 September 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LMK04208 User s Guide Figure 8 LMK04208 ...

Page 17: ...www ti com Schematics 17 SNAU200 September 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LMK04208 User s Guide Figure 9 Digital ...

Page 18: ...Schematics www ti com 18 SNAU200 September 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LMK04208 User s Guide Figure 10 Inputs ...

Page 19: ...www ti com Schematics 19 SNAU200 September 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated LMK04208 User s Guide Figure 11 Clock Outputs ...

Page 20: ...C39 C47 C48 C49 C50 C51 C52 C53 C54 C55 C57 C58 C59 C60 C63 C69 C78 C81 24 CAP CERM 0 1uF 25V 5 X7R 0603 C0603C104J3RACTU Kemet 12 C22 1 CAP CERM 0 1 µF 16 V 10 X7R 0603 C0603C104K4RACTU Kemet 13 C31 C36 2 CAP CERM 2pF 50V 12 5 C0G NP0 0603 C0603C209C5GACTU Kemet 14 C33 1 CAP CERM 1000pF 50V 5 C0G NP0 0603 C0603C102J5GACTU Kemet 15 C37 C61 C67 C73 C86 5 CAP CERM 10uF 10V 10 X5R 0805 C0805C106K8PAC...

Page 21: ...10k ohm 5 0 1W 0603 CRCW060310K0JNEA Vishay Dale 41 R27 R28 R29 3 RES 0 5 0 063 W 0402 CRCW04020000Z0ED Vishay Dale 42 R36 R39 2 RES 4 7k ohm 5 0 1W 0603 CRCW06034K70JNEA Vishay Dale 43 R44 R48 R50 R51 R54 R56 R57 R58 8 RES 15k ohm 5 0 1W 0603 CRCW060315K0JNEA Vishay Dale 44 R68 R77 R80 R87 4 RES 51 ohm 5 0 1W 0603 CRCW060351R0JNEA Vishay Dale 45 R69 R71 R72 R74 R82 R86 R89 R90 8 RES 240 ohm 5 0 1...

Page 22: ... some comments for use of the displayed screen A 1 Communication Setup Window The Communication Setup dialog is opened by selecting USB communications Interface The user may select the USB2ANY that will be used to program the device on the evaluation board If multiple USB2ANYs are connected to the same PC identify the target device by clicking the Identify button the selected USB2ANY will briefly ...

Page 23: ...ice operation mode select clock input and PLL operational frequencies The OSCin Source control doesn t control an actual register but unlinks the VCXO frequency from OSCin to allow for single PLL operation of PLL2 Likewise the selected clock input for PLL1 combobox allows the user to select which input clock to use for frequency calculations this is important for Pin Select and Auto CLKin Select m...

Page 24: ...exas Instruments Incorporated TICS Pro Usage A 3 Clock Outputs Page The Clock Distribution page allows the user to control the output channel blocks If a 0 delay mode is being used changing the clock output frequency divider or source in the feedback path may impact PLL lock Figure 14 Clock Outputs Page ...

Page 25: ... and HOLDOVER_MUX registers for controlling the status outputs These allow the user to set the status outputs to display PLL1 or PLL2 digital lock detect Other common settings are PLLX R 2 or PLLX N 2 to troubleshoot PLL locking issues This displays half the frequency at the phase detector from the R or N path Unexpected frequencies from either of these nodes will help to determine if the lock iss...

Page 26: ...gisters Page The Raw Registers page allows the user to see and directly change the bit field being used to program the device Export Register Map or File Export Hex Register Values will dump the registers to a simple txt file format which can then be used by the customer s application for programming the configured LMK04208 mode Figure 16 Raw Registers Page ...

Page 27: ... 2016 Submit Documentation Feedback Copyright 2016 Texas Instruments Incorporated TICS Pro Usage A 6 Burst Mode Page The Burst Mode page allows the user to create sequences or loops of register programming for test purposes Figure 17 Burst Mode Page ...

Page 28: ...VCO s phase noise to dominate the final output phase noise at high offset frequencies This results in the best overall noise and jitter performance Table 7 lists the test conditions used for output clock phase noise measurements with the VG 4513CA 122 8800M GFCT3 Epson VCXO Table 7 LMK04208 Test Conditions PARAMETER VALUE PLL1 Reference clock input CLKin1 single ended input CLKin1 AC coupled to GN...

Page 29: ...th for PLL1 while retaining the frequency accuracy of the reference clock input This VCXO sets the reference noise to PLL2 Figure 18 shows the open loop typical phase noise performance of the VG 4513CA 122 8800M GFCT3 Epson VCXO and CVHD 950 122 88 Crystek VCXO 120 ohm em refers to the emitter resistors of the AC coupled LVPECL output are 120 Ω Figure 18 VCXO Phase Noise at 122 88 MHz Table 8 VCXO...

Page 30: ... and 2949 12 MHz The default populated VG 4513CA 122 8800M GFCT3 Epson VCXO is used for measurements The note 240 ohm em refers to the emitter resistors of the AC coupled LVPECL output are 240 Ω B 2 1 CLKout 245 76 MHz Figure 19 LMK04208 245 76 MHz Divide by 12 Table 10 245 76 MHz Clock Output Phase Noise dBc Hz Offset LVDS SE LVDS Balun LVCMOS Norm Inv SE LVPECL16 w 240 ohm em SE LVPECL16 w 240 o...

Page 31: ...ts B 2 2 CLKout 2949 12 MHz 2949 12 MHz CLKout Figure 20 LMK04208 2949 12 MHz Divide by 1 Table 12 2949 12 MHz Clock Output Phase Noise dBc Hz Offset LVPECL16 w 240 ohm em SE LVPECL16 w 240 ohm em Balun 10 Hz 58 4 55 7 100 Hz 78 4 80 8 1 kHz 101 2 101 3 10 kHz 110 8 110 4 100 kHz 114 0 113 9 1 MHz 126 6 126 8 5 MHz 140 7 141 0 10 MHz 145 4 145 8 20 MHz 147 4 147 7 40 MHz 148 5 149 2 Table 13 2949 ...

Page 32: ...ring the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warranted for the remainder of the original warranty period Replaced EVMs shall be warranted for a new full ninety 90 day warranty period 3 ...

Page 33: ... by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la rég...

Page 34: ... connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even with the inputs and outputs kept within the specified allowable ranges some circuit components may have elevated case temperatures These components include but are not limited to linear regulators switching transistors pass transistors cu...

Page 35: ...F REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED 8 2 Specific Limitations IN NO EVENT SHALL T...

Page 36: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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