Texas Instruments LMK00725EVM, User Manual

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Operation
Jumpers:
• CLK-SEL selects between one of two inputs.
– 0 (position 1-2) = Select CLK0, nCLK0 inputs
– 1 (position 2-3) = Select CLK1, nCLK1 inputs
• CLK-EN selects between U1 clock enabled or disabled modes.
– 0 (position 1-2) = Clock Disabled
– 1 (position 2-3) = Clock Enabled (normal operation)
4 Operation
Power :
Before, applying any clock inputs, supply the board with 3.3 V and ground at VCC and GND pins of the
PWR header. Make sure the supply current being drawn is less than 115 mA.
Inputs :
Figure 1 shows the LMK00725 input structure. The internal 51 k Ω pull-up and pull-down resistors work
with the external 50 Ω termination resistors, which bias the device inputs to mid-rail. Therefore, AC-
coupled clock sources from 0.15Vpp to 1.3Vpp (50 Ω terminated) can be tied to either of the two
differential clock inputs. With the default input termination shown in Figure 1 , the input SMAs expect a 10
0 Ω differential clock source. Note that with the default input configuration, the differential input has only
very small offset voltage (~3.2 mV) so that when the selected clock inputs are left open/floating, the
outputs could have the tendency to chatter.
With DC-coupled clock sources, use a “DC-block” at the input SMAs to ensure DUT input voltage range
compliance. Alternatively, adjust the clock source DC bias (if available) to make sure the LMK00725 input
voltage range is not violated.
Figure 1. LMK00725 Input Structure and Default Input Termination
The clock inputs can accommodate a differential input or single-ended input signal with the proper
external input termination using the various component options on the board. Refer to the datasheet for
input interface application circuits.
To achieve the best possible additive jitter and noise floor performance, it is recommended to drive the
CLK/nCLK pair using an input signal with fast slew rate of 3 V/ns (differential) or higher. Driving the input
with a lower slew rate can degrade the additive jitter and noise floor performance. For this reason, a
differential input signal (e.g. LVPECL), is recommended because it typically provides higher slew rate and
common-mode noise rejection compared to a single-ended input (LVCMOS/LVTTL or sine-wave, for
example).
5 SNOU126 – September 2013 LMK00725EVM User’s Guide
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