Register Tables
5
Register Tables
Register Maps
The LMH0318 register set definition is organized into four groups:
1. Global Registers: Chip ID, Interrupt status, LOS registers
2. Receiver Registers: Equalizer boost settings and signal detect setting
3. CDR Registers: PLL control
4. Transmitter Registers: OUT0 and OUT1 parameter setting
The typical device initialization sequence for the LMH0318 includes the followings. For detailed register
settings See
LMH0318 Programming Guide
(
1. Shared Register Configuration
(a) Reading device ID
(b) Selecting interrupt on to LOS pin
(c) Settings up the register to access the channel registers
2. Channel Register Configuration
(a) CDR Reset
(b) Interrupt register configuration
(c) Optional Input/Output selection
(d) Optional VOD selection
(e) CDR Reset and Release
5.1
Global Registers
Table 5. Global Registers
FIELD REGISTER
REGISTER NAME
BITS
DEFAULT
R/RW
DESCRIPTION
ADDRESS
SMBus Observation
Reg_0x00 Share
0x00
SMBus Address Observation
7
SMBUS_addr3
0
R
SMBus strap observation
6
SMBUS_addr2
0
R
5
SMBUS_addr1
0
R
4
SMBUS_addr0
0
R
3
Reserved
0
RW
2
Reserved
0
RW
1
Reserved
0
RW
0
Reserved
0
RW
Reset Shared Regs
Reg 0x04 Share
0x01
Shared Register Reset
7
Reserved
0
RW
rst_i2c_regs
1: Reset Shared Registers
6
0
RW
0: Normal operation
5
Reserved
0
RW
4
Reserved
0
RW
3
Reserved
0
RW
2
Reserved
0
RW
1
Reserved
0
RW
0
Reserved
1
RW
Enable SMBus Strap
Reg 0x06 Share
0x00
Allow SMBus strap observation
7
Reserved
0
RW
6
Reserved
0
RW
5
Reserved
0
RW
19
SNLU183 – September 2015
LMH0318 Programming Guide
Copyright © 2015, Texas Instruments Incorporated
