Note
The watchdog or MCU error is an indication of a significant error which has taken place outside
of the PMIC. The PMIC does not actually transition through the safe recovery as with an
MCU_POWER_ERR, however, in order to maintain consistency all of the regulators are returned
to the values stored in NVM and the recovery counter is incremented. If the recovery counter exceeds
the recovery count threshold the PMICs stay in the safe recovery state.
Note
After the MCU_TO_WARM sequence the MCU is responsible for managing the EN_DRV and
recovery counter. At the end of the sequence the 'FORCE_EN_DRV_LOW' bit is cleared so that
the MCU can set the ENABLE_DRV bit.
Resource
nRSTOUT
TPS65941213-Q1
PMIC
Delay Diagram
Total Delay
Rail Name
0 us
H_MCU_PORz_1V8
BUCK4
TPS65941213-Q1
0 us
VDD_MCU_0V85
LDO2
TPS65941213-Q1
0 us
VDD_MCUIO_1V8
LDO4
TPS65941213-Q1
0 us
VDA_MCU_1V8
LDO1
TPS65941213-Q1
0 us
VDD1_DDR_1V8
nRSTOUT
TPS65941213-Q1
2000 us
H_MCU_PORz_1V8
EN_DRV
TPS65941213-Q1
0 us
EN_DRV
Figure 6-8. MCU_TO_WARM Sequence
Note
The regulator transitions do not represent enabling of the regulators but the time at which the voltages
are restored to their default values. Since this sequence originates from the MCU_ONLY state these
regulators are on.
6.3.7 TO_MCU
The TO_MCU sequence first turns off rails and GPIOs which are assigned to the SOC power group. The
sequence enables the MCU rails, in the event that they are not already active (when transitioning from
STANDBY to MCU_ONLY for example). There are two cases for this sequence, based off the value stored
in the I2C_7 register bit of primary TPS65941213-Q1 and secondary TPS65941111-Q1. The I2C_7 setting must
be the same in each PMIC before triggering the sequence. If the bits are low, then VDD1 and EN_DDR_BUCK
are disabled;
. If the I2C_7 bit is high, then VDD1 and EN_DDR_BUCK are enabled;
.
The first instructions of the TO_MCU sequence perform writes to the MISC_CTRL and ENABLE_DRV_STAT
registers.
// TPS65941213
// Set AMUXOUT_EN, CLKMON_EN
// Clear LPM_EN, NRSTOUT_SOC
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x18 MASK=0xE1
// Clear SPMI_LP_EN
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x00 MASK=0xEF
// TPS65941111
// Set AMUXOUT_EN, CLKMON_EN
// Clear LPM_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x18 MASK=0xE3
Pre-Configurable Finite State Machine (PFSM) Settings
SLVUC99 – JANUARY 2022
Optimized Dual TPS6594-Q1 PMIC User Guide for Jacinto
™
7 DRA829 or
TDA4VM Automotive PDN-0C
43
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