Other Functions
Load EVM - This button programs the CDC clock generator, loads the test pattern into the TSW3100,
loads the TgtCfg file, progams the DAC, and programs the TX and RX attenuators. This needs to be done
for both CH0 and CH1
5.8
RF Card
RF Card Version - This button selects a predetermined file which contains the information that will be
loaded into the programmable devices in the RF section of the GC5325 EVM. The default value,
“
6149_14bit_61p44bypass
”
, is used for the 14 bit ADC feedback version of EVM. The 11 bit option is used
for China configurations which is different due to export control limitations. The differences are the sample
rate and signal IF. A
“
custom
”
option can be selected, which allows the user to set custom values for the
CDCM7005 outputs. The user should not change the default setting.
Load
–
Used to load a custom configuration for the CDCM7005. Typically, this is not used.
VCXO Freq
–
Specifies the VCXO frequency to be used by the CDCM7005. The on-board VCXO is
737.28 MHz. If an external VCXO is to be used, the value needs to be entered here.
Divider Ratios - This is the divide value used by each of the CDCM7005 outputs. The first number is the
divide ratio for the FPGA clock, the second the DAC clocks, the third GC5325 DPD clocks, the fourth is
connector J49, and the last the ADC clock.
Output Enable - This is the enable value used by each of the CDCM7005 outputs. The clock is enabled
when this is set to a
“
1
”
, and disabled when set to
“
0
”
. The assignment order is the same as the Divider
ratios.
TX atten - This box is used to set the attenuation value of the TX attenuator. The range is from 0 to 31.75,
using increments of 0.25, with 0 being minimum attenuation and 31.75 the maximum attenuation.
RX atten - This box is used to set the attenuation value of the RX attenuator. The range is from 0 to 31.75,
using increments of 0.25, with 0 being minimum attenuation and 31.75 the maximum attenuation.
Loop back - This button is used for internal loop back testing using an on-board amplifier. When this is
selected, the transmit data is removed from the output SMA and re-routed to an amplifier which then feeds
this signal into the receive path. The external receive signal from the SMA is removed from this path as
well in this mode. The board will power up in this mode by default.
Ref Clk - This window is the frequency (in MHz) of the on-board reference oscillator.
DAC5682z - This section allows the user to change certain settings of the DAC5682z devices. The
“
r/w
”
button allows the user to write and read from the internal registers of the DAC
’
s. FDAC is the frequency of
the DAC clock. Interp is the interpolation setting of the DAC.
load - Used to load a custom configuration for the DAC5682Z. Typically, this is not used.
Fdac/PLL ref - Used for custom DAC PLL setting. Typically, this is not used.
PLL - Selects PLL mode or external clock for DAC's.
Soft Sync - Used to select the sync method for the DAC's.
Check lock - This button checks the status of the DAC DLL.
Offset Cal - Clicking on this button will open a new window as shown in
. This window is used to
null the LO feedthrough at RF by using the DAC5682Z offset capability. To do this, monitor the power of
the LO feedthrough at RF, select OFFSET CAL, and adjust until the LO feedthrough is minimized.
Program All - This button will load the Rf devices with the current settings inside the RF Card section.
Save - Will save the settings inside the RF Card section to a user determined file.
25
SLWU063F
–
April 2009
–
Revised April 2011
GC5325 System Evaluation Kit
Copyright
©
2009
–
2011, Texas Instruments Incorporated
