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FPD23DAEVM User's Guide

User's Guide

Literature Number: SNLU144

may 2013

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Summary of Contents for FPD23DAEVM

Page 1: ...FPD23DAEVM User s Guide User s Guide Literature Number SNLU144 may 2013 ...

Page 2: ...ution DVI and HDMI have the same electrical specifications for their TMDS and VESA DDC links output of TFP410 is routed to 19 pin HDMI type A connector Hence hooking up this board with one of the deserializer in FPD Link II III family allows evaluation of the serial link through direct observation of the video data on HDMI DVI compatible display Figure 1 1 FPD Link II III Display Adapter FPD23DAEV...

Page 3: ...ther devices used in the system such as deserializer 5 Optionally PCF8582C 2 can be populated which is connected to on board I2C bus and allows implementation of EDID 6 TFP410 allows minimization of the skew between parallel RGB data and clock signal through a control switch S1 7 TPD8S009 and TPD4E001 provide ESD protection at the output for display port 1 3 Typical Application Figure 1 2 below il...

Page 4: ... shown in LED D1 green indicates that board is correctly powered up and 3 3V 200mA supply is available at J5 4 Connect an HDMI DVI compatible display device to J4 using an HDMI cable Desired results can be observed on the display 2 2 1 Board Setup with FPD Link input In this configuration connect input to J3 and instructions below should be followed 1 Make sure RN5 RN6 RN7 and RN8 are mounted 2 To...

Page 5: ...d be followed 1 Make sure RN1 RN2 RN3 and RN4 are mounted 2 RN5 RN6 RN7 and RN8 should not be mounted to avoid stubs 3 Verify pin VSS and REF to be shorted on JP6 while using RGB888 parallel LVCMOS input Figure 2 2 FPD23DAEVM with Parallel LVCMOS input 5 SNLU144 may 2013 Quick Start Guide Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 6: ...ata Input As mentioned earlier there two input options available NOTE To ensure electrical signal compatibility 1 Board is by default configured for LVCMOS threshold of VIH min 2 31V and VIL max 0 99V for the PanelBus Transmitter TFP410 This allows using this board with deserializer VDDIO 3 3V 2 To work with low signal swings with deserializer VDDIO 1 8V change R7 to 40kΩ and R8 to 15kΩ This hardw...

Page 7: ...ort JP4 Allows access to SDA pin of TFP410 U1 U3 and DDC_D 2 Address select port for U3 JP5 It allows to select an appropriate address for U3 PCF8582C 2 not provided in the range 0x50 to 0x57 Default floating To select appropriate reference for LVCMOS inputs JP6 Default LVCMOS inputs refer to VSS It also allows strapping of parallel LVCMOS input connector pins Allows shorting schottky diode D3 if ...

Page 8: ...the S1 4 BSEL SCL LOW selects 12 bit input dual edge input external pull up on SCL line mode HIGH Enables de skew with the trim increment selected through S1 10 S1 9 This pin should be tied either to GND or to S1 3 DKEN S1 8 VDD and avoid floating input De skew function LOW Disables de skew and default trim can be accessed through I2C setting is used S1 2 Not used In this mode PD pin should be tie...

Page 9: ...582C 2 device datasheet for more details 2 Pin2 of JP3 and JP4 are connected to BSEL SCL and DSEL SDA pins of U1 TFP410 Note that to communicate with TFP410 over I2C proper settings are required on switch S1 Refer Table 3 3 3 Pin3 of JP3 and JP4 are connected to DDC_C and DDC_D lines from the HDMI connector J4 This might be useful while using the actual EDID of the display 1 Unless resistor R19 an...

Page 10: ...0Ux92x family of devices as shown below Here a specific example of DS90UH925 DS90UH926 serial link is considered however similar procedure applies to other members of DS90Ux92x family 1 Connect USB cable to DS90UH925QSEVB and launch ALP Once DS90UH925 is detected by the software as shown in Figure 4 1 click on the device name and select Pattern Generator tab Figure 4 1 Initial Window 10 Using Inte...

Page 11: ... type of display Figure 4 3 Internal Timing Spec 4 In Internal w Ext Clock mode external PCLK is required on Serializer all other signals are generated by the device itself 5 In Internal mode all signals including PCLK are generated by the device itself 11 SNLU144 may 2013 Using Internal Test Pattern Generation of 720p FPD Link III Devices Submit Documentation Feedback Copyright 2013 Texas Instrum...

Page 12: ...igure 4 4 Approximate Pixel Clock 5 Finally check on Enable Generator and observe the output on display Optionally Enable Scrolling to view changing patterns on the display Figure 4 5 Enable Generator and Scrolling 12 Using Internal Test Pattern Generation of 720p FPD Link III Devices SNLU144 may 2013 Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 13: ...Appendix A SNLU144 may 2013 Board Schematic 13 SNLU144 may 2013 Board Schematic Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 14: ...Board Stackup www ti com A 1 Board Stackup Figure A 1 Board Stackup 14 Board Schematic SNLU144 may 2013 Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 15: ...SS VSS FBIN PCLK PCLK_IN PCLK_OUT PCLK_OUT VSS Data2 Data1 Data0 Clock 3 3V VSS DSEL SDA BSEL SCL EDGE HTPLG 2 2 1 1 0 0 C C R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7 HS VS DE PCLK R5 510 1 2 O N 1 2 3 4 5 6 7 8 9 10 S1 SW 1 2 3 4 13 14 15 16 5 6 7 8 12 11 10 9 18 17 19 20 FB3 600ohm 250mA C10 22uF 1 2 RN3 RESAR_IS_8 SM 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 R34 0 1 2...

Page 16: ... 600ohm 250mA U4 DS90CF386 PDN 25 RXCLKOUT 26 RXIN0 9 RXIN0 10 RXIN1 11 RXIN1 12 RXIN2 15 RXIN2 16 RXIN3 19 RXIN3 20 RXCLKIN 17 RXCLKIN 18 RXOUT0 27 RXOUT1 29 RXOUT2 30 RXOUT3 32 RXOUT4 33 RXOUT5 34 RXOUT6 35 RXOUT7 37 RXOUT8 38 RXOUT9 39 RXOUT10 41 RXOUT11 42 RXOUT12 43 RXOUT13 45 RXOUT14 46 RXOUT15 47 RXOUT16 49 RXOUT17 50 RXOUT18 51 RXOUT19 53 RXOUT20 54 RXOUT21 55 RXOUT22 1 RXOUT23 2 RXOUT24 3...

Page 17: ...0 1 2 R25 4 7K 0603 1 2 D4 U6 REG1117 3 3 SOT VIN 3 VOUT 2 GND 1 Tab 4 JP7 1 2 J7 HEADER 4 1 2 3 4 U2 TPD4E001 IO1 1 IO4 5 VCC 6 IO3 4 IO2 2 GND 3 U7 TPD8S009 VCC 13 D3 12 GND 11 D3 10 D0 1 GND 5 D1 6 D2 7 GND 8 NC 14 D1 4 GND 2 VCC 15 D0 3 D2 9 C11 0 1uF R19 4 7K 0603 1 2 J6 CONN JACK PWR 3 2 1 C4 0 1uF JP5 1 2 3 C13 0 1uF R4 1K_NO_STUFF 1 2 C2 10uF 1 2 D1 LED R1 220 1 2 C14 0 1uF C22 1 0uF U8 TP...

Page 18: ...www ti com 18 Board Schematic SNLU144 may 2013 Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 19: ...0 1443 2 ND SMD LED SUPER RED CLR THIN 0603 1 D2 LED Red 0603_LED 160 1447 2 ND SMD DIODE MBRA210LT3GOSTR 2 D3 D4 SMA DIODE SCHOTTKY 10V 2A SMA SCHOTTKY ND FB1 FB2 FB3 FB4 FB5 600ohm 250 6 0402 587 1839 1 ND FERRITE BEAD 600 OHM 0402 FB6 mA JP1 JP2 JP3 JP4 JP5 CONN HEADER VERT 100 3POS 6 3 Pin Header Header_3P A26545 ND JP6 15AU CONN HEADER VERT 100 2POS 1 JP7 JUMPER Header_2P A26542 ND 30AU CONN ...

Page 20: ... P4 7KGCT ND SMD RES 22 0 OHM 1 10W 1 0402 2 R22 R23 22 0402 P22 0LCT ND SMD 1 R26 0 NO STUFF 0603 NO STUFF 0603 SMD DO NOT STUFF RES 100 OHM 1 10W 5 0402 5 R27 R28 R29 R30 R31 100 0402 P100JTR ND SMD RES ZERO OHM 5 0402 SMD 2 R32 R33 0 NO STUFF 0402 P0 0JTR ND DO NOT STUFF 1 R35 NO STUFF 0603 NO STUFF 0603 SMD NO STUFF 4 R37 R38 R39 R40 NO STUFF 0201 P100AGTR ND 0201 SMD DO NOT STUFF DIP_SW_10P S...

Page 21: ...s The following mechanical drawings illustrate the physical layout and stack up of the 4 layer FPD23DAEVM evaluation board Figure C 1 Top Silkscreen 21 SNLU144 may 2013 Board Layout Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 22: ...Board Layers www ti com Figure C 2 Top Layer Figure C 3 Layer 2 Ground 22 Board Layout SNLU144 may 2013 Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 23: ...www ti com Board Layers Figure C 4 Layer 3 Power Figure C 5 Bottom Layer 23 SNLU144 may 2013 Board Layout Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

Page 24: ...Board Layers www ti com Figure C 6 Bottom Silkscreen 24 Board Layout SNLU144 may 2013 Submit Documentation Feedback Copyright 2013 Texas Instruments Incorporated ...

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