1
3
5
7
9
11
13
2
4
6
8
10
12
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TEST/SBWTCK
MSP430Fxxx
RST/NMI/SBWTDIO
TDO/TDI
TCK
GND
JTAG
R1
47 kΩ
VCC TOOL
VCC TARGET
C1
1.1 nF
(See Note B)
J1 (see Note A)
J2 (see Note A)
Important to connect
V /AV /DV
CC
CC
CC
V /AV /DV
SS
SS
SS
V
CC
C2
10 µF
C3
0.1 µF
A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or
programming adapter.
B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and any
capacitance that is attached to this signal can affect the ability to establish a connection with the device. The upper limit for C1 is 2.2 nF
when using current TI tools. The typical value for SBW communication is shown. The range can vary between 0.1 nF and 2.2 nF
depending on SBW speed, voltage, and board design. See the device-specific data sheet for device-specific recommendations.
C. For extra ESD protection on the TEST pin, a 500ohm to 1k ohm pull down resistor can be added
Figure 2-3. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire) Used by All MSP430 SBW-
Capable Devices That are Not Part of F2xx, G2xx, F4xx Families
Note
On some Spy-Bi-Wire capable MSP430 devices, TEST/SBWTCK is very sensitive to rising signal
edges that can cause the test logic to enter a state where an entry sequence (either 2
‑
wire or 4-wire)
is not recognized correctly and JTAG access stays disabled. Unintentional edges on SBWTCK can
occur when the JTAG connector is connected to the target device.
Design Considerations for In-Circuit Programming
SLAU278AG – MAY 2009 – REVISED DECEMBER 2020
MSP430™ Hardware Tools
23
Copyright © 2020 Texas Instruments Incorporated
