Texas Instruments eInfochips TMDXEVM6657L, Technical Reference Manual, Page: 71 / 91

Technical Reference Manual TMDXEVM6657L
SPRUHG7 - Revised August 2012
TMDXEVM6657LE
Page 71 / 90
5.3.4 Boot Configuration Forced in I2C Boot
Note: This workaround is only needed with PG1.0 samples of the TMS320C6657 DSP. For reliable PLL
operation at boot-up, the FPGA will force the DSP to boot from the I2C by providing the boot configuration value
as 0x0405 on the boot mode pins [12:0]. After the code in the I2C SEEPROM executes to initialize the PLLs, it
will read the true values on the DIP switches from the registers in the FPGA and then boot as if the normal boot
sequence had occurred.
The exception for the forced I2C boot is the emulation boot. The FPGA will not perform the I2C boot configuration
override when the DIP switches have the following configuration: BOOTMODE[2:0] (GPIO[3:1]) = [000] and
BOOTMODE[5:4] (GPIO[6:5]) = [00]. Therefore, the additional logic of the FPGA will allow the emulation boot to
latch directly from the DIP switches.
5.4 Reset definition
5.4.1 Reset Behavior

Power-On: The Power-On behavior includes initiating and sequencing the power sources, clock sources
and then DSP startup. Please refer to the section 5.5.1 for detailed sequence and operations.

Full Reset: The RESETFULLz is asserted low to the DSP. This causes RESETSTAT# to go low which
triggers the boot configuration to be driven from the FPGA. Reset to the Marvell PHY is also asserted.
POR# and RESET# to the DSP remain high. The power supplies and clocks operate without interruption.
Please refer to the section 5.5.3 for detailed timing diagrams.

Warm Reset: The RESETz is asserted low to the DSP. The PORz and RESETFULLz to the DSP remain
high. The power supplies and clocks operate without interruption.
5.4.2 Reset Switches and Triggers

FULL_RESET (RST_FULL1) : A logic low state with a low to high transition will trigger a Full Reset
behavior event.
When the push button switch RST_FULL1 is
pressed, FPGA on EVM will assert DSP‟s RESETFULL# input
to issue a total reset of the DSP, everything on the DSP will be reset to its default state in response to this
event, boot configurations will be latched and the ROM boot process will be initiated.
This is equivalent to a power cycle of the board but POR and will have following effects:
* Reset DSP
* Reset Gigabit Ethernet PHY
* Reload boot parameters.
* Protect the contents in the I2C EEPROM, NAND flash and SPI NOR flash.

WARM_RESET (RST_WARM1): A logic low state with a low to high transition will trigger a warm reset
behavior event.
When the push button Switch RST_WARM1 is pressed, FPGA will assert a DSP RESET# input, which will
reset the DSP. Software can program this to be either hard or soft. Hard reset is the default which resets