OPEN: I2C Address = 0x30 (7'b)
GND
IDX
GND
40.2k
R27
0
R19
DNP
GND
0.1µF
C6
DNP
0.01µF
C7
DNP
GND
VDDIO
OEN/XIN/REFCLK
MODE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J2
TSW-108-07-G-D
GND
GPIO0
GPIO1
GPIO2
GPIO3/INTB
HSYNC/GPIO4
VSYNC/GPIO5
PCLK/GPIO6
GND
10k
R16
10k
R17
PDB
GND
10k
R5
DNP
4
1
2
3
J4
0022112042
GND
0
R25
0
R26
I2C_SDA
I2C_SCL
0.1µF
C34
GND
4.7k
R21
4.7k
R20
I2C_SCL
I2C_SDA
VDDIO
S2
10µF
C3
VDD1V8
VDD3V3
1
2
3
J1
TSW-103-07-G-S
OEN/XIN/REFCLK
MODE
IDX
1
2
J3
DNP
GND
GND
10.0k
R28
DNP
12pF
C37
DNP
12pF
C38
DNP
10.0k
R24
DNP
OSS_SEL/XOUT
OEN/XIN/REFCLK
0
R29
DNP
i
LABEL "REF_CLK
470
R4
GND
100k
R6
VDD3V3
Green
2
1
D1
1
2
J34
SHORTED: I2C Address = 0x3D (7'b)
VDD1V8
VDDIO
C
SI
(953
)
- Co
a
x
R
A
W
12 Lo
w
-F
req
(9
13) - Co
a
x
R
A
W
12 H
ig
h
-F
re
q
(91
3) -
C
o
a
x
R
A
W1
0 (
9
13) -
C
o
a
x
GPIO3/INTB
10k
R37
10k
R38
BISTEN
SEL
TESTEN
GND
VDDIO
120 ohm
L8
1µF
C30
0.1µF
C31
0.01µF
C32
0.01µF
C33
GND
VDD1V1
VDDFPD_1V1
GND
VDDCSI_1V1
VDDD_1V1
GND
0.01µF
C10
1µF
C8
0.1µF
C9
0.01µF
C13
1µF
C11
0.1µF
C12
0.01µF
C16
0.01µF
C17
1µF
C14
0.1µF
C15
0
R23
DNP
GND
VDD_1P8_CSI
VDD1V8
120 ohm
L1
1µF
C18
0.1µF
C19
0.01µF
C20
VDDFPD_1V8
0.01µF
C24
0.01µF
C25
1µF
C22
0.1µF
C23
1µF
C26
0.1µF
C27
0.01µF
C28
0.01µF
C29
10µF
C21
GND
VDDP_1V8
ROUT_8/CSI_D0_P
ROUT_9/CSI_D0_N
ROUT_6/CSI_D1_P
ROUT_7/CSI_D1_N
ROUT_2/CSI_D2_P
ROUT_3/CSI_D2_N
ROUT_0/CSI_D3_P
ROUT_1/CSI_D3_N
ROUT_1/CSI_D3_N
ROUT_0/CSI_D3_P
ROUT_8/CSI_D0_P
ROUT_9/CSI_D0_N
ROUT_6/CSI_D1_P
ROUT_7/CSI_D1_N
ROUT_3/CSI_D2_N
ROUT_2/CSI_D2_P
ROUT_10/CSI_CLK0_P
ROUT_11/CSI_CLK0_N
ROUT_4/CSI_CLK1_P
ROUT_5/CSI_CLK1_N
I2C_SCL
I2C_SDA
GPIO3/INTB
ROUT_10/CSI_CLK0_P
ROUT_11/CSI_CLK0_N
ROUT_4/CSI_CLK1_P
ROUT_5/CSI_CLK1_N
GPIO0
GPIO1
GPIO2
HSYNC/GPIO4
VSYNC/GPIO5
PCLK/GPIO6
GPIO0
GPIO1
GPIO2
HSYNC/GPIO4
VSYNC/GPIO5
PCLK/GPIO6
RIN0_P
RIN0_N
RIN1_P
RIN1_N
RIN0_P
RIN0_N
RIN1_P
RIN1_N
VDDIO
VDD_1P8_CSI
VDDFPD_1V8
VDDP_1V8
VDDFPD_1V1
VDDCSI_1V1
VDDD_1V1
GND
CMLOUT_P
CMLOUT_N
0.1µF
C1
0.1µF
C2
LOCK
PASS
TESTEN
BISTEN
MODE
IDX
GPIO3/INTB
VDDIO
4.7k
R22
I2C_SCL
I2C_SDA
OEN/XIN/REFCLK
OSS_SEL/XOUT
10µF
C39
10µF
C40
10µF
C41
10µF
C36
DNP
10µF
C35
DNP
PDB
PDB
MODE
BISTEN
TESTEN
IDX
OEN/XIN/REFCLK
OSS_SEL/XOUT
VDD1V8
GPIO3/INTB
SEL
SEL
MIPI_SEL
MIPI_SEL
LOCK
PASS
1
2
J36
5-146261-1
1
2
J37
5-146261-1
GND
GND
LOCK
PASS
6
3
1
8
2
7
5
4
SW1
219-4LPST
6
3
1
8
2
7
5
4
S1
219-4LPST
GND
10k
R85
10k
R84
VDDIO
OEN/XIN/REFCLK
OSS_SEL/XOUT
REMOVE R84 and R85 in CSI Mode
GND
13.3k
R14
210k
R35
56.2k
R13
68.1k
R154
137k
R34
82.5k
R153
102k
R33
0
R36
DNP
VDDFPD_1V1
0
R155
DNP
10k
R156
VDDIO
GND
0
R157
MIPI_SEL
DO NOT POPULATE CRYSTAL
1
2
3
Q1
1
2
25MHz
Y2
DNP
120 ohm
L2
DNP
120 ohm
L3
120 ohm
L4
DNP
120 ohm
L5
120 ohm
L6
DNP
22µF
C500
DNP
22µF
C501
DNP
22µF
C502
DNP
22µF
C503
DNP
22µF
C504
DNP
22µF
C505
DNP
22µF
C506
DNP
22µF
C507
DNP
22µF
C508
DNP
22µF
C509
DNP
22µF
C510
DNP
22µF
C511
DNP
22µF
C512
DNP
22µF
C513
DNP
22µF
C514
DNP
22µF
C515
DNP
22µF
C516
DNP
22µF
C517
DNP
22µF
C518
DNP
22µF
C519
DNP
22µF
C520
DNP
1
H1
BMI-S-201-F
DNP
DESERIALIZER EMI/EMC SHIELD
GND
TP16
TP17
100
R182
GND
0
R187
DNP
0
R188
DNP
0
R189
DNP
GPIO4
GPIO6
PCLK needs to be 50 ohm
GPIO4
GPIO5
GPIO5
GPIO6
i
LABEL "GPIO3/INTB"
2
3
S3B
1
4
S3A
VCC
4
E/D
1
GND
2
OUT
3
25MHz
Y1
7C-25.000MCB-T
DNP
BISTEN
6
ROUT_10/C
12
ROUT_11/CSI_CLK0-
11
ROUT_4/C
19
ROUT_5/CSI_CLK1-
18
ROUT_8/
14
ROUT_9/CSI_D0-
13
ROUT_6/
16
ROUT_7/CSI_D1-
15
ROUT_2/
22
ROUT_3/CSI_D2-
21
ROUT_0/
24
ROUT_1/CSI_D3-
23
GPIO_0
28
GPIO_1
27
GPIO_2
26
GPIO_3/INTB
25
HSYNC/GPIO_4
10
VSYNC/GPIO_5
9
PCLK/GPIO_6
8
I2C_SCL
2
I2C_SDA
1
IDX
35
LOCK
48
CMLOUTN
39
CMLOUTP
38
MODE
37
PAD
49
PASS
47
PDB
30
RIN0+
41
RIN0-
42
RIN1+
32
RIN1-
33
TESTEN
44
VDDIO
29
VDDIO
7
VDD_1P1_CSI
20
VDD_1P1_D
3
VDD_1P1_FPD
34
MIPI_SEL
43
VDD_1P8
17
VDD_1P8_FPD0
40
VDD_1P8_FPD1
31
VDD_1P8_P0
45
VDD_1P8_P1
36
SEL
46
OEN/XIN/REFCLK
5
OSS_SEL/XOUT
4
U1
DS90UB934TRGZRQ1
i VDDIO
i SCL
i SDA
i GND
0.1µF
C4
0.1µF
C5
0
R11
DNP
0
R12
DNP
0
R18
DNP
SH-J1
Assembly Note
ZZ12
Place Jumper on pins 1 and 2 for J1
MODE and IDX Resistors
are +/-1% tolerance.
Place 10uF, 1uF, 0.1uF
and 0.01uF bypass caps on
bottom of board, close to
U1 VDD pins
Layout note: For all differential pairs(CSI-2 and FPD) in this
design follow the guidelines decribed below: Route together
with controlled differential 100ohm impedance and controlled
single ended 50ohm impedance for all single ended signals
(ROUT, HS, VS, PCLK,), route with controlled single ended 50
ohm impedance. Keep away from other high speed signals.
Keep lengths within 10mil of each other. Keep traces on layers
adjacent to the ground plane. Keep the number of VIAS to
minimum. If VIAS are used, make it symetrical through all
signals. Keep diff pairs separated at least by x3 of the trace
width. NO STUBS on the signal path, components should be
placed such that the signals can be routed in pass-through
manner.
100 ohm diff pair. +/-5%.
Resistors have to be placed
close to U1.
+/- 10 mil for all inter/intra
pairs.
DS90UB934 cannot receive
external 1.1V supply - Please
keep R23 unpopulated for
DS90UB934 and populated for
DS90UB954.
C1 & C2 should be fitted
as a 0.1uF when
interfacing with
DS90UB913A &
DS90UB933. C1 & C2
fitted with 0.033uF for
interfacing with
DS90UB953.
Copyright © 2016, Texas Instruments Incorporated
PCB Schematics
21
SNLU220 – December 2016
Copyright © 2016, Texas Instruments Incorporated
Using the DS90UB934-Q1EVM Evaluation Module
7
PCB Schematics