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Setup

11

SNLU142A – May 2014 – Revised January 2016

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Copyright © 2014–2016, Texas Instruments Incorporated

DS110DF111EVM Evaluation Board

Figure 6. DS110DF111 Low Level Page

Figure 7. DS110DF111 Eye Monitor Page

For more information about functions about SigCon Architect and the retimer profiles, please reference the
"SigCon Architect: Installation and Starter's Guide" (

SNLU178

) and the "DS110DF410EVK,

DS110DF410EVK, and DS125DF410EVM Evaluation Board Software Installation, Setup, and Operating
Guide" (

SNLU126

).

Summary of Contents for DS110DF111EVM

Page 1: ...DS110DF111EVM Evaluation Board User s Guide Literature Number SNLU142A May 2014 Revised January 2016...

Page 2: ...as Instruments Incorporated Table of Contents Contents 1 Overview 4 2 Features 5 3 Applications 5 4 Ordering Information 5 5 Setup 6 5 1 Pin Control Mode 6 5 2 SMBus Slave Mode 9 5 3 EEPROM Mode 12 6...

Page 3: ...VM Slave Mode Close Up 9 5 DS110DF111 High Level Page 10 6 DS110DF111 Low Level Page 11 7 DS110DF111 Eye Monitor Page 11 8 DS110DF111 EEPROM Hex File Generation Page 12 9 Top Assembly Layer 13 10 Bott...

Page 4: ...VM SMA evaluation kit provides a complete high band width platform to evaluate the signal integrity and signal conditioning features of the Texas Instruments signal conditioning products with Equaliza...

Page 5: ...sis Driver to 12 dB Low Power Consumption 200 mW Channel Locks to Half Quarter Eighth Data Rates for Legacy Support On chip Eye Monitor EOM PRBS Generator Input Signal Detection CDR Lock Detection Ind...

Page 6: ...in the design This EVM and documentation focus on Pin Control and SMBus Slave Mode to highlight the ease of use and excellent low jitter performance of the DS110DF111 5 1 Pin Control Mode In Pin Contr...

Page 7: ...eration INA to OUT A and INB to OUT B 6 J91 VODA 1 k to GND L 600 mV output VOD on OUT A 7 J10 VODB 1 k to GND L 600 mV output VOD on OUT B 8 J41 DEMA 1 k to GND L 0 dB De emphasis on OUT A 9 J51 DEMB...

Page 8: ...os 4 and 8 a pre set equalization level is used 5 1 4 Loopback J6 and J61 control the DS110DF111EVM loopback function according to Table 4 Table 4 DS110DF111 Loopback Control Loopback Mode of Operatio...

Page 9: ...supply to this pin 4 Floating the AD 1 0 inputs will result in an SMBus Address 00 30 h 5 J3 ENSMB H SMBus Slave Mode 6 Connect the board signals SDA SCL and GND on J20 to a DPS DONGLE EVM or an equiv...

Page 10: ...Any registers not described in the datasheet tables should be treated as Reserved The user should not try to write new values to these registers The user accessible registers described in the datashee...

Page 11: ...ard Figure 6 DS110DF111 Low Level Page Figure 7 DS110DF111 Eye Monitor Page For more information about functions about SigCon Architect and the retimer profiles please reference the SigCon Architect I...

Page 12: ...tartup settings from a programmed EEPROM in the 8 pin DIP socket U2 SigCon Architect can be used to generate an EEPROM Hex file by configuring the EEPROM page settings Figure 8 DS110DF111 EEPROM Hex F...

Page 13: ...0DF111EVM The EVM uses simple 100 mil headers to control the output signal integrity functions The DS110DF111EVM is very compact and low power the board traces have been designed for connection to sta...

Page 14: ...C11 0 22 R16 1K SMA5 142 0771 821 SIG 1 GND 2 GND 3 GND 4 GND 5 R15 1K J51 WM6502 ND 1 2 J3 WM6503 ND 1 2 3 R2 20K J41 WM6502 ND 1 2 J91 WM6502 ND 1 2 SMA2 142 0771 821 SIG 1 GND 2 GND 3 GND 4 GND 5 R...

Page 15: ...J18 TERM QF 052 DIA 250 STURDY MT Keystone 1287 ST 7 J3 J4 J5 J6 J9 J19 J20 CONN HEADER 3 POS 0 100 VERT GOLD Molex WM50016 03 ND 7 J14 J41 J51 J61 J91 J141 J161 CONN HEADER 2 POS 0 100 VERT GOLD Mole...

Page 16: ...110DF111EVM Evaluation Board 9 Example Waveforms With the default power up configuration the DS110DF111 is designed to LOCK to 10 3125 Gbps or 1 25 Gbps encoded data The results in Figure 11 and Figur...

Page 17: ...le Waveforms 17 SNLU142A May 2014 Revised January 2016 Submit Documentation Feedback Copyright 2014 2016 Texas Instruments Incorporated DS110DF111EVM Evaluation Board Figure 12 10 3125 Gbps RjDj Jitte...

Page 18: ...ed source formatting of Pin Control descriptions 6 Deleted DS110DF111 pin map from Pin Control Mode Configuration subsection 7 Changed connection to reflect operation with SigCon Architect through the...

Page 19: ...ing the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repa...

Page 20: ...transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indic...

Page 21: ...ified allowable ranges some circuit components may have elevated case temperatures These components include but are not limited to linear regulators switching transistors pass transistors current sens...

Page 22: ...REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE L...

Page 23: ...sponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related inf...

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