Texas Instruments DP83561EVM, User Manual, Page: 13 / 60

Table 3-2. DP83561-SP 4-Level Bootstrap Resistor Designation and Suggested Bootstrap Resistor Values
PIN NAME
PIN
NUMBER
STRAP NAME
STRAP
MODE
PU RESISTOR
(KΩ)
PU RESISTOR
DESIGNATION
PD RESISTOR
(KΩ)
PD RESISTOR
DESIGNATION
RX_D0 44 PHY_ADD[1:0]
1 OPEN
R152
OPEN
R154
2 10 2.49
3 5.76 2.49
4 2.49 OPEN
RX_D1 45 PHY_ADD[3:2]
1 OPEN
R155
OPEN
R158
2 10 2.49
3 5.76 2.49
4 2.49 OPEN
Table 3-3. DP83561-SP 2-Level Bootstrap Selection and Jumper Designation
PIN NAME PIN NUMBER STRAP NAME
STRAP
MODE
JUMPER
PLACEMENT
JUMPER
DESIGNATION
VDDIOSEL_0 22 VDDIOSEL_0
0 OPEN
J36
1 CLOSED
VDDIOSEL_1 21 VDDIOSEL_1
0 OPEN
J35
1 CLOSED
SUPPLYMODE_SEL 23 SUPPLYMODE_SEL
0 OPEN
J37
1 CLOSED
CRS/GPIO_3 33 RGMII/MII_SEL
0 OPEN
J41
1 CLOSED
AUTO_RECOVER 34 AUTO_RECOVER
0 OPEN
J39
1 CLOSED
RX_CTRL 48 MIRROR_EN
0 OPEN
J31
1 CLOSED
SMI_DISABLE 50 SMI_DISABLE
0 OPEN
J40
1 CLOSED
POWERGOOD 59 POWERGOOD
0 OPEN
N/A
1 CLOSED
Table 3-4. DP83561-SP LED Bootstrap Selection and Jumper Designation
PIN NAME PIN NUMBER STRAP NAME STRAP MODE JUMPER PLACEMENT JUMPER DESIGNATION
LED_0 63 ANED_DIS
0 OPEN/PD
J28
1 PU
LED_1 62 ANEGSEL_0
0 OPEN/PD
J33
1 PU
LED_2 45 ANEGSEL_1
0 OPEN/PD
J38
1 PU
3.2.2 Mirror Mode
The DP83561EVM enables Mirror Mode by default. As can be observed in Section 8.4 , due to the RJ45
orientation and routing on the board, the differential transmit and receive pairs orientation and polarity have been
flipped on J27. Mirror mode must be enabled to correct this change, unless the link partner uses a similar routing
and layout strategy, matching the differential pairs correctly.
3.3 Clock Selection
3.3.1 On-Board 25 MHz Crystal
By default, the DP83561 is configured to use the on-board 25 MHz crystal. To verify the on-board 25 MHz crystal
is properly connected, confirm the following:
www.ti.com Board Setup Details
SLVUC11 – APRIL 2021
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DP83561EVM User’s Guide 13
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