AARDVARK
CONNECTOR
Three place switches - hi, lo, no connect
Sampled at POR
I2C_EN_HI
I2C_EN_LO
PRE_SEL_HI
PRE_SEL_LO
EQ_SEL_HI
EQ_SEL_LO
SLEW_CTL_HI
SLEW_CTL_LO
SWAP_POL_HI
SWAP_POL_LO
SIG_EN_HI
SIG_EN_LO
TX_TERM_CTL_HI
TX_TERM_CTL_LO
VCC_3P3V
VCC_3P3V
VCC_3P3V
VCC_3P3V
VCC_3P3V
VCC_3P3V
VCC_3P3V
VCC_3P3V
VCC_3P3V
I2C_EN_PIN
PAGE3
PRE_SEL
PAGE3
EQ_SEL_A0
PAGE3
SLEW_CTL
PAGE3
SCL_CTL
PAGE3
SDA_CTL
PAGE3
SWAP/POL
PAGE3
HDMI_SEL#_TEST_A1
PAGE3
SIG_EN
PAGE3
TX_TERM_CTL
PAGE3
SDA_CTL_USB
PAGE8
SCL_CTL_USB
PAGE8
VSADJ
PAGE3
R76
PTV09 10K POT
R61
65K
0402
5%
R57
65K
0402
5%
R69
65K
0402
5%
J14
HDR3X1 M .1
TX_TERM_CTL
LO
HI
1
2
3
J12
HDR3X1 M .1
EQ_SEL_A0
LO
HI
1
2
3
R68
65K
0402
5%
R65
65K
0402
5%
R62
65K
0402
5%
R70
65K
0402
5%
J7
HDR3X1 M .1
HDMI_SEL#/TEST/A1
LO
HI
1
2
3
R115
47K
0402
5%
R71
65K
0402
5%
R72
65K
0402
5%
R60
65K
0402
5%
R59
2K
0402
5%
R67
65K
0402
5%
J17
HDR3X1 M .1
SWAP/POL
LO
HI
1
2
3
J8
HDR3X1 M .1
DEFAULT
VSADJ
POT
1
2
3
R66
65K
0402
5%
J10
HDR3X1 M .1
SLEW_CTL
LO
HI
1
2
3
J4
HDR3X1 M .1
SCL
SCL_USB
SCL_AAR
1
2
3
R58
2K
0402
5%
R75
7K
0402
1%
R63
65K
0402
5%
R64
65K
0402
5%
R73
65K
0402
5%
J15
HDR3X1 M .1
PRE_SEL
LO
HI
1
2
3
R74
65K
0402
5%
J5
Header 5x2 0.1" thru-hole
AARDVARK I2C
2
4
6
8
10
1
3
5
7
9
J6
HDR3X1 M .1
SDA
SDA_USB
SDA_AAR
1
2
3
J11
HDR3X1 M .1
SIG_EN
LO
HI
1
2
3
J3
HDR3X1 M .1
I2C_EN_PIN
LO
HI
1
2
3
EVM Schematics
17
SLLU225A – August 2015 – Revised March 2018
Copyright © 2015–2018, Texas Instruments Incorporated
DP159RGZ Evaluation Module
Figure 10. DP159RGZEVM Select Options