HDVPSS Pressure
Generation
HDVPSS VPDMA Descriptor
Pressure[1]
(Mflag[1])
Pressure[0]
(Mflag[0])
MReqPriority[2] MReqPriority[1] MReqPriority[0]
HDVPSS
INIT_PRESSURE_0
Pressure Bits Used in Interconnect Arbitration
Priority Bits Used in EMIF Arbitration
Internal Modules
241
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.2.13.3.1.4.1 Packet Type
Bits 31:27 are a unique code which indicates that this Descriptor is a VPDMA descriptor. This value
should be 0xA for data transfer descriptor.
1.2.13.3.1.4.2 Mode
Bit 26 is used to indicate if the transfer is to regular memory space or to 2D TILED memory space. The
VPDMA will use this to determine if it does standard raster based addressing or if it assumes that the data
is stored in TILER format. If data is stored in TILER format then the buffer is turned into 2 or 4 line buffers
depending on the container type. For shared clients, such as the ancillary data and the VIP port, that use
the memory only one can be active if the mode field is set.
1.2.13.3.1.4.3 Direction
Bit 25 is used to indicate the direction of transfer. This bit indicates that the data flow is from an external
source to an internal buffer (inbound) or data transfers form an internal buffer to an external location
(outbound).
1.2.13.3.1.4.4 Channel
Bits 24:16 are the Channels which is supported by the descriptor. This is the identification of the specific
Channel that is controlled by the contents of the descriptor. The channel assignments can be found in the
channel table.
1.2.13.3.1.4.5 Priority
The priority bits (Bits 11, 10 and 9) are used to set the priority at the EMIF level.
VPDMA has two master ports (mst0 and mst1) to transfer the data to external and internal memories.
The priority level for the VPDMA masters can be at two different levels: L3 level (for all the transfers), and
EMIF level (only for DDR transfers), as shown in
.
Figure 1-168. HDVPSS Pressure and Priority Settings
