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P1

P0

P2

PIXCLK

HSYNC

DATA

VSYNC

FID

ACTVID

P1

P0

P2

PIXCLK

HSYNC

DATA

VSYNC

FID

ACTVID

Internal Modules

148

SPRUHI7A – December 2012 – Revised June 2016

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Copyright © 2012–2016, Texas Instruments Incorporated

High-Definition Video Processing Subsystem (HDVPSS)

Following the vertical blanking region, the video portion of the field or frame starts.

shows the

horizontal blanking area in this video portion of the field or frame. P0 is the first pixel in the horizontal
blanking. HSYNC is active for one or more pixel clocks. VSYNC is inactive in this video area. FID can
change here. ACTVID is low since P0 is horizontal blanking.

Figure 1-93. Type 1, Horizontal Blanking in Video Region

In

, P0 represents the first Chroma pixel in the Active video line. HSYNC is inactive, since P0

is in the active video region. Likewise, VSYNC is inactive. FID may or may not change here. ACTVID is
high to signal capturing of video pixels.

Figure 1-94. Type 1, First Video Pixel

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Summary of Contents for DM38x DaVinci

Page 1: ...DM38x DaVinci Digital Media Processor High Definition Video Processing Subsystem HDVPSS User s Guide Literature Number SPRUHI7A December 2012 Revised June 2016...

Page 2: ...le 72 1 2 4 Constrained Image Generator CIG 79 1 2 5 Graphics Module GRPX 82 1 2 6 Standard Definition Video Encoder SD_VENC 94 1 2 7 High Definition Video Encoder HD_VENC 128 1 2 8 VIP Parser 140 1 2...

Page 3: ...a Left aligned 61 1 17 Catmull Rom Filter Definition 62 1 18 Definition of X 62 1 19 Anchor Pixels 62 1 20 4 2 0 Interlaced Scan 63 1 21 Ideal 4 2 2 Chroma Upsampling for Interlaced Scan 63 1 22 Matri...

Page 4: ...70 VBI I F Vertical Timing 124 1 71 DAC I F Logic 127 1 72 HD VENC Block Diagram 129 1 73 Vertical Sync Signals for OSD 130 1 74 Horizontal Sync related Signal for OSD 130 1 75 Video Data Interface B...

Page 5: ...ion of a Period 164 1 117 Channel ID Inserted Into Horizontal Blanking 167 1 118 Vertical Ancillary Data Cropping Region 171 1 119 Active Video Region 171 1 120 Discrete Sync Interface Signals 172 1 1...

Page 6: ...Conditions Where Valid Configurations May Not Work in a System 231 1 165 Example 232 1 166 Inbound Data Transfer Descriptor Format 236 1 167 Outbound Data Transfer Descriptor Format 236 1 168 HDVPSS...

Page 7: ...reg0 Register 317 1 212 CHR_US_reg1 Register 318 1 213 CHR_US_reg2 Register 319 1 214 CHR_US_reg3 Register 320 1 215 CHR_US_reg4 Register 321 1 216 CHR_US_reg5 Register 322 1 217 CHR_US_reg6 Register...

Page 8: ...intc_intr0_ena_clr1 Register 386 1 267 intc_intr1_status_raw0 Register 388 1 268 intc_intr1_status_raw1 Register 390 1 269 intc_intr1_status_ena0 Register 392 1 270 intc_intr1_status_ena1 Register 394...

Page 9: ...nt0_channel1_int_mask Register 478 1 317 VPDMA_int0_channel2_int_stat Register 481 1 318 VPDMA_int0_channel2_int_mask Register 485 1 319 VPDMA_int0_channel3_int_stat Register 488 1 320 VPDMA_int0_chan...

Page 10: ...ister 619 1 363 VPDMA_int2_channel5_int_stat Register 622 1 364 VPDMA_int2_channel5_int_mask Register 626 1 365 VPDMA_int2_channel6_int_stat Register 629 1 366 VPDMA_int2_channel6_int_mask Register 63...

Page 11: ...gister 726 1 411 VPDMA_vip1_lo_uv_cstat Register 727 1 412 VPDMA_vip1_up_y_cstat Register 728 1 413 VPDMA_vip1_up_uv_cstat Register 729 1 414 VPDMA_vip2_lo_y_cstat Register 730 1 415 VPDMA_vip2_lo_uv_...

Page 12: ...75 1 458 HD_VENC_D_cfg21 Register 776 1 459 HD_VENC_D_cfg22 Register 777 1 460 HD_VENC_D_cfg23 Register 778 1 461 HD_VENC_D_cfg24 Register 779 1 462 HD_VENC_D_cfg25 Register 780 1 463 HD_VEND_D_GAMMA_...

Page 13: ...NC_dtvs7 Register 831 1 509 SD_VENC_tvdetgp0 Register 832 1 510 SD_VENC_tvdetgp1 Register 833 1 511 SD_VENC_irq0 Register 834 1 512 SD_VENC_estat Register 835 1 513 SD_VENC_ectl Register 836 1 514 SD_...

Page 14: ...ER_main Register 889 1 564 VIP_PARSER_port_a Register 890 1 565 VIP_PARSER_xtra_port_a Register 893 1 566 VIP_PARSER_port_b Register 894 1 567 VIP_PARSER_xtra_port_b Register 897 1 568 VIP_PARSER_fiq_...

Page 15: ...rc7_size Register 935 1 599 VIP_PARSER_output_port_b_src8_size Register 936 1 600 VIP_PARSER_output_port_b_src9_size Register 937 1 601 VIP_PARSER_output_port_b_src10_size Register 938 1 602 VIP_PARSE...

Page 16: ...figuration descriptor payload word 0 3 84 1 19 Region Configuration Attribute Inbound data descriptor word 4 7 85 1 20 Blending and Transparency Configuration 88 1 21 Region Scaler Configuration Attri...

Page 17: ...es 205 1 72 Memory Databus Write Order 235 1 73 Data Packet Descriptor Word 0 Field Descriptions 237 1 74 Data Packet Descriptor Word 1 Field Description 239 1 75 Data Packet Descriptor Word 2 Field D...

Page 18: ...escriptions 318 1 119 CHR_US_reg2 Register Field Descriptions 319 1 120 CHR_US_reg3 Register Field Descriptions 320 1 121 CHR_US_reg4 Register Field Descriptions 321 1 122 CHR_US_reg5 Register Field D...

Page 19: ...tatus_raw0 Register Field Descriptions 372 1 171 intc_intr0_status_raw1 Register Field Descriptions 374 1 172 intc_intr0_status_ena0 Register Field Descriptions 376 1 173 intc_intr0_status_ena1 Regist...

Page 20: ...462 1 219 VPDMA_bg_rgb Register Field Descriptions 463 1 220 VPDMA_bg_yuv Register Field Descriptions 464 1 221 VPDMA_descriptor_top Register Field Descriptions 465 1 222 VPDMA_descriptor_bottom Regis...

Page 21: ...ns 589 1 266 VPDMA_int2_channel0_int_mask Register Field Descriptions 592 1 267 VPDMA_int2_channel1_int_stat Register Field Descriptions 594 1 268 VPDMA_int2_channel1_int_mask Register Field Descripti...

Page 22: ...tions 717 1 314 VPDMA_pip_wrbk_cstat Register Field Descriptions 718 1 315 VPDMA_sc_in_chroma_cstat Register Field Descriptions 719 1 316 VPDMA_sc_in_luma_cstat Register Field Descriptions 720 1 317 V...

Page 23: ...ions 766 1 362 HD_VENC_D_cfg12 Register Field Descriptions 767 1 363 HD_VENC_D_cfg13 Register Field Descriptions 768 1 364 HD_VENC_D_cfg14 Register Field Descriptions 769 1 365 HD_VENC_D_cfg15 Registe...

Page 24: ...ister Field Descriptions 819 1 413 SD_VENC_vmod Register Field Descriptions 820 1 414 SD_VENC_slave Register Field Descriptions 821 1 415 SD_VENC_size Register Field Descriptions 822 1 416 SD_VENC_pol...

Page 25: ...ptions 867 1 461 SD_VENC_dacsel Register Field Descriptions 868 1 462 SD_VENC_dupf0 Register Field Descriptions 869 1 463 SD_VENC_dupf1 Register Field Descriptions 870 1 464 SD_VENC_dactst Register Fi...

Page 26: ...escriptions 928 1 510 VIP_PARSER_output_port_b_src1_size Register Field Descriptions 929 1 511 VIP_PARSER_output_port_b_src2_size Register Field Descriptions 930 1 512 VIP_PARSER_output_port_b_src3_si...

Page 27: ...mplemented on the device Reserved for future device expansion Reserved for TI testing Reserved configurations of the device that are not supported Writing non default values to the Reserved bits could...

Page 28: ...t 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS Chapter 1 SPRUHI7A December 2012 Revised June 2016 High Definition Video Processing Subsystem HDVPSS Topic...

Page 29: ...ating Line SC Scaler SD Standard Definition SDK Software Development Kit COMP Compositor VENC Video Encoder VIP Video Input Port VPDMA Video Port Direct Memory Access FID Field ID Modules inside HDVPS...

Page 30: ...l for details Scan format conversions that is interlaced to progressive and vice versa is supported Especially the interlaced to progressive conversion will employ a high quality motion adaptive 3D de...

Page 31: ...MI or DVO2 pixel clock 1 1 3 6 Video Output and Encoding Features A single HDMI 1 3 compliant interface with HDCP to support 1080p 1080p 24 30 and 60 are mandatory 1080i 720p 480p 480i 640x480 800x600...

Page 32: ...xed streams Up to 1920x1200 60Hz 160MHz input data rate is supported for 16 bit mode input port Each video capture port supports one scaler capable of both up and down scaling of one non multiplexed i...

Page 33: ...ck paths of the primary and auxiliary deinterlacers Write back of the scaled video from main aux or additional video input source video channels supports both tightly 1 frame per 1 display frame perio...

Page 34: ...the instance numbering for the VIP and GRPX submodules as VIP0 VIP1 and GRPX0 GRPX1 GRPX2 However the register sections use the numbering VIP1 VIP2 and GRPX1 GRPX2 GRPX3 The following list is the conv...

Page 35: ...ame buffer RGB All types of RGB formats described in VPDMA section 422S 422 Semi planar tiled non tiled separate Luma and Chroma buffers Cb Cr interleaved in Chroma buffer www ti com Description of th...

Page 36: ...Motion Data To From VPDMA 7 Primary Video Fn Input Path From VPDMA 8 Primary Video Fn 1 Input Path From VPDMA 9 Primary Video Fn 2 Input Path From VPDMA 10 Bypass Path 0 Input BP0 From VPDMA 11 Bypass...

Page 37: ...f the interconnect and selections possible within the Video Input Ports In Figure 1 4 the signals shown on the Video Input Port Parser VIP_PARSER module are the outputs generated by this module Extern...

Page 38: ...d sc_src_select 0 Mux path disabled csc_src_select 0 Mux path disabled rgb_out_hi_select rgb_src_select chr_ds_1_bypass rgb_out_hi_select rgb_out_hi_select chr_ds_1_bypass chr_ds_2_bypass 0 1 3 4 5 6...

Page 39: ...upon the client that it services Based on this four kinds of channel has been defined YUV Channel Clients taking data in YUV format like DEI NF and so on RGB Channel Clients taking RGB data like GRPX...

Page 40: ...2 VCOMP Mux The video compositor VCOMP module takes two inputs MAIN and PIP The MAIN input comes from Primary Input Path and PIP input can be selected from one of three sources Auxiliary Input Path A...

Page 41: ...this path is disabled meaning no PIP input 1 1 5 10 PIP Display Input The HD Composite VENC path can come from 1 of 3 sources The Auxiliary Input Pipe or from either of the Bypass 422 pipes non tiled...

Page 42: ...he Auxiliary Input DEI Video Input Port 1 When the source of the Video Input Port Color Space Converter is set to one of the DEI inputs this mux will pass the output of the Color Space Converter out i...

Page 43: ...VPDMA section 422S 422 Semi planar tiled non tiled separate Luma and Chroma buffers Cb Cr interleaved in Chroma buffer www ti com Description of the Subsystem 43 SPRUHI7A December 2012 Revised June 2...

Page 44: ...vip1 mux select 0 1 1 6 2 Tri Display There are several display configurations for the Tri Display format The first configuration Figure 1 6 shows the auxiliary video path on the SD display In this ca...

Page 45: ...0 nf_bypass HD DAC BLEND HD VENC_A VBI IF CHR_US P2 CHR_US_P1 CHR_US_P0 4 CHR_US_SEC0 CHR_US_SEC1 422S 422S 420T 422P 420 Semi planar tiled non tiled separate Luma and Chroma buffers Cb Cr interleaved...

Page 46: ...0 nf_bypass HD DAC BLEND HD VENC_A VBI IF CHR_US P2 CHR_US_P1 CHR_US_P0 4 CHR_US_SEC0 CHR_US_SEC1 422S 422S 420T 422P 420 Semi planar tiled non tiled separate Luma and Chroma buffers Cb Cr interleaved...

Page 47: ...ain disable 3 2 1 dvo2_select 1 3 2 4 7 sdvenc_select 1 0 1 0 1 0 nf_bypass HD DAC BLEND HD VENC_A VBI IF CHR_US P2 CHR_US_P1 CHR_US_P0 4 CHR_US_SEC0 CHR_US_SEC1 422S 422S 420T 422P 420 Semi planar ti...

Page 48: ...ister Value Required vcomp mux select 1 hdcomp mux select 1 sd mux select 2 sc_5 mux select 1 sec0 mux select 0 sec1 mux select 0 csc_vip0 mux select 0 sc_vip0 mux select 4 chr_ds0_vip0 mux select 0 c...

Page 49: ...sdvenc_select 1 0 1 0 1 0 nf_bypass HD DAC BLEND HD VENC_A VBI IF CHR_US P2 CHR_US_P1 CHR_US_P0 4 CHR_US_SEC0 CHR_US_SEC1 422S 422S 420T 422P 420 Semi planar tiled non tiled separate Luma and Chroma b...

Page 50: ...ister Value Required vcomp mux select 1 hdcomp mux select 1 sd mux select 2 sc_5 mux select 1 sec0 mux select 0 sec1 mux select 0 csc_vip0 mux select 0 sc_vip0 mux select 4 chr_ds0_vip0 mux select 3 c...

Page 51: ...420 Semi planar tiled non tiled separate Luma and Chroma buffers Cb Cr interleaved in Chroma buffer 422 Interleave non tiled Luma and Chroma Interleaved in the same buffer RGB All types of RGB format...

Page 52: ...ister Value Required vcomp mux select 1 hdcomp mux select 1 sd mux select 2 sc_5 mux select 1 sec0 mux select 0 sec1 mux select 0 csc_vip0 mux select 0 sc_vip0 mux select 0 chr_ds0_vip0 mux select 3 c...

Page 53: ...Addresses 1 2 3 4 5 6 7 8 SC_M GRPX CIG cf BLEND sc_m_wrbk_select vcomp_pip_select 1 2 3 4 5 6 7 1 2 3 0 1 vcomp_main disable 3 2 1 dvo2_select 1 3 2 4 7 sdvenc_select 1 0 1 0 1 0 nf_bypass HD DAC BLE...

Page 54: ...ister Value Required vcomp mux select 1 hdcomp mux select 1 sd mux select 2 sc_5 mux select 1 sec0 mux select 0 sec1 mux select 0 csc_vip0 mux select 0 sc_vip0 mux select 0 chr_ds0_vip0 mux select 3 c...

Page 55: ...Interrupt Name INTRx Mapped Processor MMR Address Offset Range 0 INTR0 Cortex A8 0x20 0x3F 1 INTR1 GEM 0x40 0x5F 2 INTR2 Media controller processors 0x60 0x7F 3 INTR3 Media controller processors 0x80...

Page 56: ...rrupt Status Raw Set register 1 1 7 3 Mask OFF Enable Interrupt Interrupt Enable Set register is used to disable the MASK for selected signals in Interrupt Status Raw Set register Writing 1 to a bit f...

Page 57: ...DMA VPDMA VPDMA VPDMA VPDMA int0_list0_int_stat 12 int0_list0_int_mask 12 vpdma_int0_list6_complete_raw int0_list0_int_stat 13 int0_list0_int_mask 13 vpdma_int0_list6_notify_raw int0_list0_int_stat 14...

Page 58: ...el6_int_mask vpdma_int0_channel_group6_raw int0_client0_int_stat 31 0 and int0_client1_int_stat 29 0 int0_client0_int_mask 31 0 and int0_client1_int_mask 29 0 vpdma_int0_client_raw VPDMA VPDMA dei_err...

Page 59: ...ks In HDVPSS some of the data paths and modules are divided into different clock domains This enables the user to switch off the paths modules that are not used at HDVPSS level The CLKC CLKC Module Cl...

Page 60: ...dules The following sequence is used to reset the entire HDVPSS module 1 Take VPDMA to standby via force standby MMR write This disconnects master ports 2 Ensure all VENCs are disabled via MMR writes...

Page 61: ...fficients corresponding to top and bottom field must be identical Each coefficient is 14 bit 4 10 format Default filter coefficients are based on Catmull Rom algorithm Capable of removing the half pel...

Page 62: ...mines the characteristics of the filter a is generally used because the filter will produce an interpolated output that is an exact match to a linear input curve In the literature some people have not...

Page 63: ...ines are scanned from the top of the picture to the bottom 1 2 1 2 1 For Interlaced YUV420 Input Data Figure 1 20 shows how 4 2 0 video is split into top and bottom fields in interlaced format Chroma...

Page 64: ...ty resulting in increasing quality can be employed to deal with chroma pixels near the edges In this module the edge pixels can be mathematically approximated using the same filter as the rest of the...

Page 65: ...following video source types 4 2 2 input progressive or interlaced input VPDMA line mode 1 CHR_US_reg0 cfg_mode 0x1 mode B CHR_US coefficients are not used in this mode so values are don t care 4 2 0...

Page 66: ...D0 Cb A1 R B1 G C1 B D1 Cr A2 R B2 G C2 B D2 Using YUV to RGB conversion as an example YUV represents one color space and RGB represents another color space The conversion can be written in the matri...

Page 67: ...Conversion from RGB to YCbCr Figure 1 23 Conversion from RGB to YCbCr Conversion from YCbCr to RGB Figure 1 24 Conversion from YCbCr to RGB 1 2 2 2 1 2 HDTV Application with Graphics Data Range The t...

Page 68: ...F45 C1 13 bit 0 5114 524 0x020C C1 13 bit 0 4577 469 0x1E2B A2 13 bit 0 5114 524 0x020C A2 13 bit 1 1024 0x0400 B2 13 bit 0 4646 476 0x1E24 B2 13 bit 1 8142 1858 0x0742 C2 13 bit 0 0468 48 0x1FD0 C2 1...

Page 69: ...cation with Video Data Range The two equations presented in this section are for the SDTV application The chromaticity parameters are defined by ITU R601 standard The input video data for these equati...

Page 70: ...V Application with Graphics Data Range The two equations presented in this section are for the SDTV application with graphics range data input The main application is for computer graphics display The...

Page 71: ...x1EA7 C1 13 bit 0 511 523 0x020B C1 13 bit 0 6984 715 0x1D35 A2 13 bit 0 511 523 0x020B A2 13 bit 1 1024 0x0400 B2 13 bit 0 428 438 0x1E4A B2 13 bit 1 7336 1775 0x06EF C2 13 bit 0 083 85 0x1FAB C2 13...

Page 72: ...os and three graphics to generate one composite output layer The SD blender can take up to four input layers one video and three graphics to generate one composite output layer This is shown in Figure...

Page 73: ...ose the right format If the graphics module has interlaced input it can only provide interlaced output through progressive data path Therefore the interlaced input data path can not be used in this ca...

Page 74: ...les Please note that it does NOT imply any restriction on the actual input video sizes in external memory to be the same For example Video 0 can be 1920x1080 and Video 1 can be 720x480 in the memory C...

Page 75: ...ip is configured in COMP VENC settings The VENC _vid_bld_ord bitfield is described in the video alpha blender section 1 2 3 3 2 HD PIP Video Window CIG module forms the PIP video window after receivin...

Page 76: ..._pos_y y Background color for Grpx window is transparent and carries an alpha value of zero It gets the background color set by COMP back_clr at the time of composition The alpha value configuration f...

Page 77: ...by COMP VENC settings VENC _vid bld_ord bitfield The alpha values for both the videos are configured in CIG module as described in the sections above The alpha value blended alpha of the blended video...

Page 78: ...er flow to the VENC Hence the feedback path needs to be given proper high priority in the system for memory access when the corresponding VENC is also functional Both the paths feedback path and Venc...

Page 79: ...ection capable of transmitting content in High Definition Analogue Form to a Constrained Image The basic requirement of a constrained image is that it contains the visual equivalent of not more than 5...

Page 80: ...al direction and to later recover the original display size The CIG module performs decimation in both vertical and horizontal directions to achieve the resolution reduction by th in vertical in horiz...

Page 81: ...lacing is also supported on this path just in case the incoming video is in progressive scan mode but it needs to be fed into interlaced output Note that all W H X Y configurations need to be in FRAME...

Page 82: ...ing box support to reduce artifacts at region boundaries 1 2 5 2 Functional Description GRPX module reads a RGB or bitmap image data and applies the frame region attributes to create a graphics plane...

Page 83: ...Output Port Interlaced Output Port Region Attributes Region Data COMP Stencil Data GRPX VPDMA ARGB MASK BIT SCALE_EN LUT_TYPE 1 1 www ti com Internal Modules 83 SPRUHI7A December 2012 Revised June 20...

Page 84: ...r example if GRPX0 output is used in DVO2 display output then GRPX0 frame configuration parameters should be same as DVO2 display output frame size Table 1 18 Frame Configuration Attribute Configurati...

Page 85: ...0 68 Reserved Disp_first_region 71 1 First region of the frame Disp_last_region 72 1 First region of the frame scaler_enable 73 Scaler enable Reserved 74 Reserved stenciling_en 75 Stenciling enable fo...

Page 86: ...direction from top of the frame Region2 in Figure 1 38 is the last region in the frame 1 2 5 2 2 1 4 Scaler The scaler used in GRPX module is consisted of a 5 tap 8 phase horizontal and a 4 tap 8 phas...

Page 87: ...mplementation When a region is scaled up or down the poly phase vertical filter will inherently provide anti flicker filtering Even when a region is not needed to be scaled the scaler can still be ena...

Page 88: ...a comparison to TRANS_COLOR 10 Mask 1 0 11 Mask 2 0 Example If TR_LSB_MASK is set to 2 b11 top 5 bits of R G B component data are compared to the corresponding 5 bits of TRANS_COLOR R G B color 101 Tr...

Page 89: ...izontal TAP 0 Phase 6 Reserved 111 106 reserved coefh0_p7 121 112 Coefficient for Horizontal TAP 0 Phase 7 Reserved 127 122 reserved Table 1 22 Region Scaler Attributes 2 Attribute Bits Description co...

Page 90: ...scription coefh3_p0 9 0 Coefficient for Horizontal TAP 3 Phase 0 Reserved 15 10 reserved coefh3_p1 25 16 Coefficient for Horizontal TAP 3 Phase 1 Reserved 31 26 reserved coefh3_p2 41 32 Coefficient fo...

Page 91: ...fineoffsethorz 30 16 Count offset for start of line Reserved 127 31 Reserved Table 1 27 Region Scaler Attributes 7 Attribute Bits Description coefv0_p0 9 0 Coefficient for Vertical TAP 0 Phase 0 Reser...

Page 92: ...its Description coefv2_p0 9 0 Coefficient for Vertical TAP 2 Phase 0 Reserved 15 10 reserved coefv2_p1 25 16 Coefficient for Vertical TAP 2 Phase 1 Reserved 31 26 reserved coefv2_p2 41 32 Coefficient...

Page 93: ...or start of line Reserved 127 31 Reserved 1 2 5 2 5 VPDMA Configuration VPDMA needs to be setup to configure the GRPX module and input data transfer The initialization sequence for each frame assuming...

Page 94: ...wide screen 16 9 aspect ratios ITU R BT 1119 Wide screen signaling for broadcasting Signaling for wide screen and other enhanced television parameters EIAJ CPR 1204 Transfer Method of Video ID informa...

Page 95: ...video output 1 2 6 2 Functional Description 1 2 6 2 1 Block Diagram Figure 1 40 VENC Block Diagram 1 2 6 2 2 Operating Modes 1 2 6 2 2 1 Synchronous Mode The VENC supports two synchronous modes maste...

Page 96: ...t 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS Figure 1 41 Example of Multiple VENC Synchronization 1 2 6 2 3 Timing 1 2 6 2 3 1 Video Timing The video ti...

Page 97: ...output combination from two DACs is described in Section 1 2 6 2 14 2 1 2 6 2 3 2 Input I F Timing The input I F consist of venc_dtv_hs horizontal sync venc_dtv_vs vertical sync venc_dtv_fid field ID...

Page 98: ...1 32 33 34 35 36 37 521 522 523 524 0V Base FID DTV_FID_V_STA1 12 1 2H DTV_FID_F_STA1 1 venc_dtv_vs 517 518 519 520 515 516 venc_dtv_avid venc_dtv_avid Internal Modules www ti com 98 SPRUHI7A December...

Page 99: ...l Modules 99 SPRUHI7A December 2012 Revised June 2016 Submit Documentation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS 1 2 6 2 3 3 Int...

Page 100: ...Modules www ti com 100 SPRUHI7A December 2012 Revised June 2016 Submit Documentation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS 1 2 6...

Page 101: ...input video timing They are independent Serration and equalization pulses are inserted on the appropriate lines defined in the standard Color burst is automatically inserted on the appropriate lines...

Page 102: ...25 8 22 20 21 264 273 284 271 CVBS HS VS FID CVBS HS VS FID top field bottom field 3H SVSW 0 3H 3H AV_V_STA0 34 1 2H AV_V_STP0 519 1 2H 3H SVSW 0 3H 3H AV_V_STA1 34 1 2H AV_V_STP1 519 1 2H TV V Counte...

Page 103: ...truments Incorporated High Definition Video Processing Subsystem HDVPSS Figure 1 53 and Figure 1 54 show the DAC video output pipeline delay against the internal base counter The pipeline delay latenc...

Page 104: ...efinition Video Processing Subsystem HDVPSS Figure 1 55 and Figure 1 56 show the non interlaced operation for 262p and 312p Table 1 34 shows the register setting for the non interlaced format Although...

Page 105: ...ge shaping is enabled and disabled Figure 1 57 Horizontal Blanking Shaping 1 2 6 2 3 7 Slave Mode Timings 1 2 6 2 3 7 1 Slave Mode Horizontal Timing Figure 1 58 shows slave mode horizontal timing The...

Page 106: ...0 25H 0 25H 0 25H 1H bottom field top field hdin vdin Base V Counter hdin Base V Counter vdin 0 5H 0 5H 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 Internal Modules www ti com 106 SPRUHI7A December 2012 Revised Ju...

Page 107: ...2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS Figure 1 61 Interlaced Slave Vertical Timing FMD 3 1 2 6 2 3 7 3 Slave Mode Field Detection For slave interf...

Page 108: ...ember 2012 Revised June 2016 Submit Documentation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS Figure 1 62 Field Detection Mode In opti...

Page 109: ...med so that it can convert the full range RGB to the desired color format Table 1 35 Color Bar Table Color G B R White 255 255 255 Yellow 255 0 255 Cyan 255 255 0 Green 255 0 0 Magenta 0 255 255 Red 0...

Page 110: ...is 13 bit s 8 4 and the output offset E is 13 bit s 12 0 The parameters in the equation A B C D and E are programmable Since the CSC output directly contributes the output video amplitude the coeffic...

Page 111: ...truments Incorporated High Definition Video Processing Subsystem HDVPSS 1 2 6 2 7 2 NTSC PAL Encoding 1 2 6 2 7 2 1 YUV Generation First YUV data should be generated by an appropriate color space conv...

Page 112: ...B R M Internal Modules www ti com 112 SPRUHI7A December 2012 Revised June 2016 Submit Documentation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsyst...

Page 113: ...4 169 157 1 163 246 83 0 64 291 56 347 0 Y Y G S U A B V R G B R M www ti com Internal Modules 113 SPRUHI7A December 2012 Revised June 2016 Submit Documentation Feedback Copyright 2012 2016 Texas Inst...

Page 114: ...4095 3 1000 878 10 1400 Y LSB A mV mV S LSB Sync mV mV 1 0 255 0 351 68 179 1 173 261 88 64 308 60 368 Y Y G S U A B V R G B R M Internal Modules www ti com 114 SPRUHI7A December 2012 Revised June 20...

Page 115: ...M 1 0 255 0 326 63 166 180 1 160 242 82 0 64 286 56 342 0 Y Y G S U A B V R G B R M www ti com Internal Modules 115 SPRUHI7A December 2012 Revised June 2016 Submit Documentation Feedback Copyright 201...

Page 116: ...the input from CSC in s 12 0 and outputs s 12 0 The chroma LPF takes s 11 0 from the CSC MSB thrown away and output s 11 0 The coefficient register format is s 0 7 The sampling rate of the FIR filter...

Page 117: ...luma The sync tip level and the sync amplitude are programmable as shown in Figure 1 64 The color burst is inserted onto the chroma The amplitude of the color burst is specified by CBLVL register as...

Page 118: ...are shown in Table 1 40 Table 1 40 Sub carrier Increment Parameters TV Format SCP0 SCP1 SCP2 Frequency NTSC M J 135 25 33 3 579545454 MHz NTSC 4 43 168 2516 16875 4 433618749 MHz PAL B D G H K I 168 2...

Page 119: ...ruments Incorporated High Definition Video Processing Subsystem HDVPSS 1 2 6 2 7 3 SECAM Encoding 1 2 6 2 7 3 1 DbDr Generation First SECAM YDbDr need to be generated using the CSC In this example the...

Page 120: ...Definition Video Processing Subsystem HDVPSS 1 2 6 2 7 3 2 Low Frequency Pre Emphasis The YDbDr from CSC is applied to the LPF for a proper attenuation The LPF function is already described in Section...

Page 121: ...sub carrier parameter register SCP1 and SCP2 respectively as shown in Figure 1 66 Figure 1 66 Sub carrier Parameter Registers The amplitude of the FM modulated sub carrier is specified by the CBLVL r...

Page 122: ...he WSS symbol is automatically determined as five seventh 5 7 of white 100 As described earlier the white level is calculated by the sync amplitude and picture sync ratio registers CSLVL and CPSR for...

Page 123: ...can be inserted using raw VBI data insertion mode In this mode the VBI waveform is synthesized by software according to the waveform requirements of the selected data type The VBI_IF module sends VBI...

Page 124: ...263 264 265 266 267 268 269 270 0H clk2x TV H Counter venc_vbi_req vbi_venc_val vbi_venc_data DAC Video Output 1 clk D0 D1 Dx D0 D1 Dx Number of samples are specified by VBI I F SW 0 1 2 3 4 5 241 168...

Page 125: ...ine of Active Video AV_V_STA0 0x8c 12 0 34 34 45 34 45 45 34 45 Vertical Stop Line of Active Video AV_V_STP0 0x8c 28 16 519 519 620 519 620 620 519 620 Vertical Start Line of Active Video AV_V_STA1 0x...

Page 126: ...t The 2x DAC oversampling eases the external analog filter cost as it can eliminate the unwanted image around the sampling frequency of clk2x Setting DAUPS enables 2x oversampling The oversampling fil...

Page 127: ...E registers The corresponding DAC should be enabled by setting these registers to 1 Otherwise DAC should be in power down state Both DACs can be power down independently By default these registers are...

Page 128: ...or Programmable Color Space Converter 10 bit data path Gamma correction table A triple channel 10 bit current steering DAC to support both Component and VGA output 1 2 7 2 Functional Overview HD VENC...

Page 129: ...eld in interlace mode It will toggle between 1 and 0 on every frame in progressive mode Programmability controlled by register CFG13 END_F1 and CFG10 LINES dtv_vs Vertical sync signal This signal is a...

Page 130: ...RUHI7A December 2012 Revised June 2016 Submit Documentation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS The following figures illustra...

Page 131: ...inition Video Processing Subsystem HDVPSS Figure 1 75 is the OSD to encoder data bus timing diagram ACT_VID is the active video data qualification signal Encoder will capture data from OSD after one c...

Page 132: ...ation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS 1 2 7 3 2 OSD Interface Configuration for Progressive Display Figure 1 76 illustrate...

Page 133: ...6 Submit Documentation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS 1 2 7 3 3 OSD Interface Configuration for Interlace Display Figure...

Page 134: ...Table 1 46 DVO Formats Formats DVO_D0 DVO_D1 DVO_D2 Single stream 656 YCbCr Unused Unused Dual stream 656 Y CbCr Unused Tri stream 656 Y G Cb B Cr R YUV422 20bit output with discrete sync Y CbCr Unus...

Page 135: ...ard panels seamlessly To archive this goal the DVO of the device has been refined with ultimate flexibility meanwhile maintaining simplicity for the software programming Following subsections present...

Page 136: ...136 SPRUHI7A December 2012 Revised June 2016 Submit Documentation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS 1 2 7 5 3 2 DVO Interfa...

Page 137: ...rmat 1 2 7 7 VBI Data Service Following are the commonly used VBI data services on analog component video interface these functions are supported by the hardware inside the encoder Type A and Type B d...

Page 138: ...e number to register VBI_L1 These VBI data line encoders can support up to two VBI lines in a frame or a field If the host CPU updates the VBI data registers at the frame rate or field rate the encode...

Page 139: ...resses for Configuration Register and LUT Memories Descriptions Start Address 12 0 End Address 12 0 HD VENC MMR 0x0000 0x0FFF LUT RAM 0x1000 0x1FFF Gamm module can be bypassed by setting CFG0 BYPS_GC...

Page 140: ...Clock Input Domains can be individually configured in any combination of Embedded or Discrete Sync Vertical ancillary data is supported for each input source For discrete sync modes where vertical anc...

Page 141: ...n scan lines in found in analog video BT 601 uses various sync signals to specify when a new field and a new line starts BT 656 and BT 1120 uses sync words embedded in the data stream to specify start...

Page 142: ...etween the EAV and SAV is equivalent to Horizontal Blanking The period between the SAV to the next EAV is active video or vertical blanking In the BT 656 or BT 1120 embedded code word scheme three bit...

Page 143: ...pairs being stored The Ancillary Data buffer is different than the Active Video Frame Buffers The Ancillary Data buffer only stores Vertical Blanking Ancillary Data The number of lines in the Ancilla...

Page 144: ...data luma and chroma data for YUV422 format capture R G and B data for RGB888 format capture is muxed for the interface modes described below 1 2 8 2 4 1 8b Interface Mode In 8b data interface mode th...

Page 145: ...Mode The three components are packed into the data bus and sent to the VPDMA The 24 bit Luma VPI client to the VPDMA carries all three components This data is saved to the DDR in packed mode That is t...

Page 146: ...enabled for either discrete or embedded sync Discrete sync basic mode is used to determine the type of vertical blanking signal DISCRETE_BASIC_MODE 0 means that the vertical blanking interval is speci...

Page 147: ...e In this diagram and all others in this document the active polarities of the interface signals can be either high or low For the sake of uniformity in this document all polarities are drawn active h...

Page 148: ...horizontal blanking area in this video portion of the field or frame P0 is the first pixel in the horizontal blanking HSYNC is active for one or more pixel clocks VSYNC is inactive in this video area...

Page 149: ...g device wants the receiving end to capture Vertical Ancillary Data using 4 pin signaling is shown in Figure 1 95 Figure 1 95 4 Pin Reduced ACTVID Signaling with Vertical Ancillary Data Figure 1 96 de...

Page 150: ...UV VPI ports respectively to the VPDMA When using HSYNC signaling instead of ACTVID the VSYNC signal may be derived from an analog source such as an NTSC PAL decoder In this case VSYNC may not transi...

Page 151: ...om Internal Modules 151 SPRUHI7A December 2012 Revised June 2016 Submit Documentation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS Figu...

Page 152: ...e pixel where the FIELD ID signal transitions can be quite variable and depends on the external chip driving the VIP Parser Many parts that generate digitized raw video have a programmable feature to...

Page 153: ...ndicator as described in Figure 1 97 In this case no FIELD ID signal is sent by the source chip A description of Field ID determination by VSYNC skew is shown in Figure 1 102 The active polarity of VS...

Page 154: ...rtical blanking interval for the beginning of the second field VSYNC has already been active for half of Line 263 For the second field VSYNC will go inactive midway through Line 282 to indicate that L...

Page 155: ...in Figure 1 97 all blanking pixels are captured However the horizontal ancillary data is byte by byte distributed between the Luma and Chroma frame buffers Chroma sited bytes are saved in the Chroma f...

Page 156: ...shown in Figure 1 106 Figure 1 106 Progressive Frame Vertical Blanking Ancillary Data Storage 1 2 8 2 6 BT 656 Style Embedded Sync 1 2 8 2 6 1 Data Input Like Discrete Sync Input Embedded Sync mode t...

Page 157: ...FF The second and third bytes are 0x00 The bit ordering of the fourth byte is detailed in Table 1 55 Table 1 55 Fourth Byte of EAV SAV Code Word 7 fixed 6 F 5 V 4 H 3 P3 V H 2 P2 F H 1 P1 F V 0 P0 F V...

Page 158: ...error condition is detected but it is non correctable Table 1 56 Error Correction Matrix P3 P2 P1 P0 F V and H Flags 000 001 010 011 100 101 110 111 0000 000 000 000 n c 000 n c n c 111 0001 000 n c...

Page 159: ...1 2 8 2 6 4 Embedded Sync Ancillary Data With Embedded Sync streams only Vertical Ancillary Data can be extracted The Vertical Ancillary Data buffer is the same width as the corresponding Luma and Chr...

Page 160: ...CbCr buffer and a planar Vertical Ancillary Data buffer RGB streams on the other hand are stored in a packed R G B format as shown in Figure 1 110 The BT 1120 standard defines a method of carrying RG...

Page 161: ...he interface pixel clock rates are shown The VPDMA limits 16 camera sources to be saved to DDR per Pixel Clock Input Domain 1 Blanking pixels are not used in the CIF clock rate calculations Addition o...

Page 162: ...d is in all four sources Like 2 Way Multiplexing the sizes of the four camera sources are the same and the sizes of the Vertical Ancillary Data regions are the same The four streams are not necessaril...

Page 163: ...ixels With the 5158 s SAVs and EAVs having the V flag always set to 0 the older DSPs would never advance their buffer pointer Hence there is a dummy vertical blanking line The external device would in...

Page 164: ...of Line EOL flags tag a split line as described in Table 1 58 Table 1 58 Split Line Table BOL EOL Function 0 0 Undefined 0 1 Line Segment is the second half of a line 1 0 Line Segment is the first ha...

Page 165: ...byte should never be 1 1 2 8 2 7 10 TI Line Mux Mode Split Lines and Channel ID Remapping The VIP Parser supports a maximum of 8 different Channel IDs per Port The Channel IDs must be in the range 0...

Page 166: ...e supported Obviously error correction cannot be performed on the FVH flags since the protection bits are no longer there Table 1 61 Channel ID Embedded in EAV SAV 7 fixed 6 F 5 V 4 H 3 ch_id 3 2 ch_i...

Page 167: ...able 1 62 Valid Embedded Sync Mux Mode and Data Bus Width Combinations 1x Mux 2x Mux 4x Mux Line Mux 8 Bit 16 Bit n a n a 24 Bit n a n a n a 1 2 8 2 10 Interrupts The VIP parser provides one interrupt...

Page 168: ...tput size for Srcnum 0 on Port A differs from the SRC0_NUMLINES and SRC0_NUMPIX register settings PrtBDisConn Port B Link Disconnect for Srcnum 0 PrtBConn Port B Link Connect for Srcnum 0 PrtADisConn...

Page 169: ...the clipping feature can be either embedded sync or discrete sync Embedded sync streams use 2 reserved codewords as sync codes 0x00 and 0xFF These sync codes define different regions in the incoming...

Page 170: ...il it sends out an end frame pixel and the downstream module accepts the end frame pixel 1 2 8 2 16 Picture Size Interrupt Each VIP port can be set up to trigger an interrupt if the picture size varie...

Page 171: ...is twice the equivalent number of Luma pixels per line In other words for this particular dual channel capture example if there are 720 Luma pixels per line then the total number of Vertical Ancillary...

Page 172: ...ntal blanking is the same number of pixels whether the line is in the active video region or in the vertical blanking region of the scan actvid is the region of a line that is active video It is exact...

Page 173: ...hsync transitions active for fast pixel clock rates since a system clock cycle is needed to insert a new frame indicator into the frame buffer Figure 1 121 vsync and hblank Input Signals 1 2 8 2 18 2...

Page 174: ...tvid Pixel will be saved only when actvid is active Note that vsync must transition active between the actvid delineated data vsync cannot transition active when actvid is active Figure 1 123 vsync an...

Page 175: ...lements on pixel clock s active edge will appear in ancillary data buffer and when vblank is inactive all data elements on pixel clock s active edge will appear in video data buffer Figure 1 125 vblan...

Page 176: ...18 7 Line and Pixel Capture Examples When DISCRETE_BASIC_MODE 0 vblank is used All the lines where the start of line is under an active vblank are sent to the Ancillary Data buffer All the lines where...

Page 177: ...em HDVPSS The start of line is the pixel represented by the inactive to active transition on actvid when USE_ACTVID_HSYNC_N 0 Note that actvid stays active for the entire duration of active video port...

Page 178: ...e VIP 7 Bad external video cable which causes corrupted video streams going into the VIP Items 6 and 7 are typically seen as noise events where it is likely that multiple horizontal syncs per line and...

Page 179: ...ware function Bad Edit Detection BED The module can pass the inputs data directly to the outputs in a bypass configuration No internal processing is performed 1 2 9 2 Functional Description The follow...

Page 180: ...accumulates difference between two neighboring frames two top fields or two bottom fields difference between two adjacent fields and combing artifact At the end of DEI data processing an interrupt wi...

Page 181: ...y to perform blending for chroma is slightly different than for luma because the MV is based on luma and extra care needs to be taken when blending is applied to chroma At this mode edge directed inte...

Page 182: ...om 182 SPRUHI7A December 2012 Revised June 2016 Submit Documentation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS Figure 1 131 VPDMA Tr...

Page 183: ...vectors In the previously listed ports except Y and UV current and Scalar output current referred to as main data all the other ports directly interact with DEI through VPDMA and are referred to as au...

Page 184: ...ntire frame size is used and the interrupt will occur at the end of the field Software services the interrupt and then applies lock and jam MMR controls to put the design in film mode This must occur...

Page 185: ...e video If the filters are too weak the noise may be still obvious If the filters are too strong edges and details may be blurred and ghosting artifacts may appear Noise levels may vary a lot within a...

Page 186: ...RUHI7A December 2012 Revised June 2016 Submit Documentation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS Figure 1 133 Noise Filter Arch...

Page 187: ...stimation For each tile the noise level tileNoise is the average of absolute pixel differences between the input frame I and the previous output frame Ip In the averaging the absolute pixel difference...

Page 188: ...scaled by spatial_strength Threshold spatial_strength Frame_noise_filtered 0 is the offset of the motion vs blending factor function It is controlled by the total noise level Total_Frame_noise as show...

Page 189: ...ck of each tile s noise output and generates a frame noise at the end of last tile processing 1 2 10 3 6 Video Source Multiplexing The hardware has 32 sets of frame noise registers to allow video sour...

Page 190: ...through the IIR filter Clear the initialization flags at Frame 1 nf_frame_noise_init_en 0 At this point to read the measured noise levels Set frame_noise_read_index 12 Read stored Frame_noise_y u v t...

Page 191: ...d right sides Input image trimmer for pan scan support Pre scaling peaking filter for enhanced sharpness Scale field as frame Interlacing of scaled output Full 1080p input and output support YCbCr422...

Page 192: ...r video write back data paths in the HDVPSS module Scaling is performed in following three steps 1 Trimming and Pre peaking filtering 2 Vertical Scaling Polyphase Running Average Filter 3 Horizontal p...

Page 193: ...bin Cbout Crin Crout www ti com Internal Modules 193 SPRUHI7A December 2012 Revised June 2016 Submit Documentation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Pro...

Page 194: ...ferent sets of coefficients are shown in Figure 1 143 If the source of the input video is NTSC or PAL format the peaking filter can be configured to reject the color subcarrier frequency Figure 1 143...

Page 195: ...odules are not available 1 2 11 2 3 1 1 Polyphase Filter Selection The scaler SC uses 5 tap polyphase filtering for vertical up scaling Figure 1 146 Vertical Polyphase Scaler Block Diagram SC 1 2 11 2...

Page 196: ...ma soft switch delta_ev_thr 4 1 Range of luma soft switch based on edge vector delta_luma_thr 4 4 Range for luma soft switch based on pixel differences max limit 8 delta_chroma_thr 4 4 Range for chrom...

Page 197: ...efficients selected based on the mod_scale_factor calculated as shown below from one of nine different sets of coefficients 8 9 10 11 12 13 14 15 16 16 if scale_factor 1 2 dcm_2x 0 dcm_4x 0 mod_scale_...

Page 198: ...sing Subsystem HDVPSS 1 2 11 2 4 1 Half Decimation Filter The half decimation filter is an 11 tap filter with following coefficients 14 0 29 0 79 128 79 0 29 0 14 For processing left and right edge pi...

Page 199: ...ht src inner col left src inner col srcWi 480 tarWi 1080 www ti com Internal Modules 199 SPRUHI7A December 2012 Revised June 2016 Submit Documentation Feedback Copyright 2012 2016 Texas Instruments In...

Page 200: ...on Source Width tarW 11 Target Width linear 1 Scaler Mode If linear 1 srcWi srcW and tarWi tarW Else srcWi srcH and tarWi tarH sc_bypass 1 0 enable scaler 1 bypass scaler auto_hs 1 Auto_hs dcm_2x dcm_...

Page 201: ...n 4 when cfg_dcm_2x 0 cfg_dcm_4x 1 nlin_left Ltar 11 if linear 1 nlin_right tarW 1 else nlin_right Ltar tarWi 1 nlin_right Rtar 11 if linear 1 nlin_left 0 nlin_acc_inc 11 24 if tarW srcW 1 then d 0 if...

Page 202: ...VS vertical polyphase scaler Luma and Chroma 5tap or 3tap VS vertical bilinear scaler top line Luma and Chroma 7tap VS vertical bilinear scaler bottom line Luma and Chroma 7tap Only the SC_H requires...

Page 203: ...ient value is 13 bits wide and takes a single half word Thus one VPI Control write carries one phase s worth of coefficients The last half word in a quad word is not used for 7tap coefficients Figure...

Page 204: ...156 shows the memory map of the VPI Control Read As the VPI Control Read has only 32 bit data bus it requires the word addressing while the write does the quad word addressing The VS top and bottom co...

Page 205: ...g ppfcoef_scale_eq_1_32_phases_ver_5tap_flip dat 15 16 ppfcoef_scale_eq_15div16_32_phases_ver_5tap_flip dat 14 16 ppfcoef_scale_eq_14div16_32_phases_ver_5tap_flip dat 13 16 ppfcoef_scale_eq_13div16_32...

Page 206: ...ile based on the width height VS vsc_file0 mod_ppfcoef_scale_eq_1_32_phases_flip dat vsc_file0 ppfcoef_scale_eq_1_32_phases_flip_PPF3_peak5_gain_eq_1_25 dat VS VER mod_tarH interlace_i 0 interlace_o 1...

Page 207: ...write_coef hsc_file0 write_coef vsc_ver_file0 write_coef vsc_ver_file0 write_coef vsc_file0 write_coef vsc_file0 sub write_coef my filename _ open INFILE dir filename or die ERROR Cannot open dir file...

Page 208: ...eaking Filter Configuration HPF Coef y_peak_enable 0 peak_select 0 0 peak at fs 4 1 NTSC 2 PAL switch peak_select case 0 peak at fs 4 and gain 1 HPF_coef0 0 HPF_coef1 0 HPF_coef2 0 HPF_coef3 4 HPF_coe...

Page 209: ...ata srcH tarH is frame height for progressive data vertical scaler typical parameters invert_field_ID 0 invert field ID input ver_pixel_offset 0 0 User may modify this is required uv_intp_thr pixel_sc...

Page 210: ...e_internal_defaults enable_edge_detection 1 sc_factor_rav 0 delta_rav 0 row_acc_init_rav 0 row_acc_init_b_rav 0 progressive or top field row_acc_offset int 65536 0 ver_pixel_offset 0 5 row_acc_inc int...

Page 211: ...scale factor 6 4 Horizontal PolyPhase Settings lin_acc_inc int 16777216 0 double mod_srcWi 1 double tarWi 1 0 5 col_acc_offset int 16777216 0 hor_pixel_offset 0 5 nlin_left tarW tarWi 1 nlin_right nli...

Page 212: ...Threshold 4 CFG_SC17 DeltaEdgeVectorThreshold 1 CFG_SC18 ConfidenceFactorDefault 0x100 CFG_SC19 0xFC000000 CFG_SC20 0x0C840800 CFG_SC21 0x00100010 CFG_SC22 0x00040190 1 2 11 4 Coefficient Data Files 1...

Page 213: ...21 275 805 780 244 25 23 258 789 789 258 23 0 25 244 780 805 275 21 10 27 229 768 816 292 18 12 28 214 754 828 308 15 13 29 200 740 838 325 12 14 30 185 726 847 343 8 15 31 172 711 856 360 4 16 31 15...

Page 214: ...33 1070 756 29 53 11 76 309 1058 782 42 56 9 77 285 1045 806 56 58 8 77 262 1030 831 71 61 6 77 239 1015 855 86 64 5 76 218 997 877 103 66 4 75 196 980 899 120 68 3 74 176 961 920 138 70 72 156 940 94...

Page 215: ...4 131 6 1 131 413 1342 562 130 9 3 130 378 1336 600 127 12 4 128 343 1328 639 123 15 5 125 309 1319 677 119 18 6 122 277 1306 716 113 22 7 118 245 1292 754 106 26 8 114 214 1276 793 98 31 8 109 185 12...

Page 216: ...276 135 17 8 161 565 1447 314 141 16 10 160 521 1454 353 146 16 12 157 477 1458 393 150 15 1 2 11 4 1 8 ppfcoef_scale_eq_14div16_32_phases_flip dat 7 32 11 27 158 370 1570 370 158 27 27 150 324 1568 4...

Page 217: ...5 23 212 1094 1307 170 0 6 27 217 1036 1354 153 7 8 30 219 978 1399 134 15 9 33 220 919 1442 113 24 11 35 219 859 1481 88 33 13 37 217 799 1518 61 43 15 38 213 740 1551 32 53 17 39 207 681 1580 0 64...

Page 218: ...57 386 734 637 234 52 373 729 648 246 46 360 725 659 258 41 347 719 670 271 37 335 713 680 283 32 322 707 690 297 314 710 710 314 0 297 690 707 322 32 283 680 713 335 37 271 670 719 347 41 258 659 725...

Page 219: ...114 75 469 819 562 123 69 453 816 577 133 63 438 813 592 142 57 422 809 607 153 51 407 805 622 163 46 391 801 636 174 41 376 795 650 186 37 361 789 664 197 32 347 782 678 209 28 332 775 691 222 25 31...

Page 220: ...9 63 84 531 867 496 70 1 2 11 4 2 6 ppfcoef_scale_eq_7_32_phases_flip dat 5 32 11 53 510 922 510 53 47 490 922 529 60 41 470 921 549 67 36 451 918 569 74 32 431 915 588 82 27 412 910 608 91 23 393 905...

Page 221: ...0 2 78 659 957 350 4 69 637 965 371 6 61 614 972 392 9 53 592 978 413 12 46 570 982 435 15 40 547 985 457 19 34 524 987 479 24 1 2 11 4 2 6 2 ppfcoef_scale_eq_9div16_32_phases_ver_5tap_flip dat 5 32 1...

Page 222: ...38 15 65 848 995 156 16 53 822 1017 174 18 43 793 1037 194 19 33 765 1056 215 21 24 737 1072 237 22 16 707 1088 260 23 9 678 1101 283 23 3 648 1113 308 24 3 618 1124 333 24 7 588 1132 359 24 11 558 11...

Page 223: ...3 1152 875 31 18 55 1122 912 23 16 38 1090 950 14 14 23 1056 986 3 9 1015 1015 9 0 3 986 1056 23 14 14 950 1090 38 16 23 912 1122 55 18 31 875 1152 73 21 39 836 1182 93 24 44 797 1208 114 27 49 757 12...

Page 224: ...2 543 93 34 94 1491 594 97 30 66 1468 645 101 25 41 1439 697 104 22 17 1408 751 106 18 4 1373 804 107 15 23 1336 857 107 12 40 1296 910 106 9 55 1253 962 103 7 67 1208 1013 99 5 78 1161 1064 94 86 111...

Page 225: ...38 90 35 82 392 1654 125 41 75 342 1665 163 47 68 293 1673 204 54 ppcoef_scale_1x_ver_5tap dat 5 32 11 0 0 2048 0 0 40 133 1785 225 55 33 91 1778 276 64 27 53 1765 330 73 21 18 1747 386 82 15 13 1722...

Page 226: ...4 18 5 102 65 1843 370 102 21 4 101 42 1812 424 101 24 3 99 20 1776 480 99 27 2 96 3 1730 539 96 30 1 93 12 1679 602 93 34 1 90 26 1627 665 90 37 0 87 37 1568 732 87 41 0 84 46 1506 801 84 45 0 80 54...

Page 227: ...es Supported Flexible placement of Main and Auxiliary layers on the background color Main and Auxiliary layers can be cropped in both horizontal and vertical directions Configurable background color i...

Page 228: ...Definition Video Processing Subsystem HDVPSS Pixels where the Main and Aux overlap are controlled by a global configuration bit VCOMP reg9 cfg_main_aux_n_ontop that determines whether the Main or the...

Page 229: ...eg3 cfg_aux_native_numpix_per_line Aux_H_skip VCOMP reg4 cfg_aux_skip_numpix Aux_H_use VCOMP reg4 cfg_aux_use_numpix Aux_V VCOMP reg3 cfg_aux_native_numlines Aux_V_skip VCOMP reg5 cfg_aux_skip_numline...

Page 230: ...und is sent out Figure 1 163 In the last case either the Main or the Aux inputs must still be sending data into the VCOMP even though the picture data is not used Figure 1 161 Main Layer Only Figure 1...

Page 231: ...external memory and is generally used to setup HD Main Video Window for display operations through VENC A VENC with a timebase generator determines the VCOMP s output timing requirements for when it n...

Page 232: ...l v supported pip034 720 main_native 250 150 x main_crop 400 200 480 v v 600 aux_native 200 80 x aux_crop 300 150 400 v v 720 display_output 100 50 x main 201 100 200 x aux 480 v 1pixel v NOT supporte...

Page 233: ...List Manager then schedules a DMA transaction to fetch the firmware and sets the list_attr rdy bit after the firmware loading is complete The followingcode is required to be included after the VPDMA...

Page 234: ...contain any kind of descriptor without limitation and be of any size The VPDMA Controller works on lists of descriptors In this mode the processor writes the lists of descriptors in the order it want...

Page 235: ...s the beginning or a burst on the quad word data bus and the arrangement of each word address within the burst Table 1 72 Memory Databus Write Order 127 96 95 64 63 32 31 0 Quadword Addr 0 Word Addr 0...

Page 236: ...e Width Frame Height Horizontal Start Vertical Start Client Specific Attributes Client Specific Attributes Address Internal Modules www ti com 236 SPRUHI7A December 2012 Revised June 2016 Submit Docum...

Page 237: ...h ARGB32 8888 8h RGBA24 6666 9h RGBA32 8888 20h Bitmap 8 22h Bitmap 4 Lower 23h Bitmap 4 Upper 24h Bitmap 2 Offset0 25h Bitmap 2 Offset1 26h Bitmap 2 Offset2 27h Bitmap 2 Offset3 28h Bitmap 1 Offset0...

Page 238: ...e Table 1 105 1 2 13 3 1 1 1 1 Miscellaneous Data Type The Data Type selects the size in bits of the data for the Miscellaneous channel The range is from 0 to 63 to represent the sizes from 1 to 64 bi...

Page 239: ...the DMA controller to skip lines for interlaced data in a progressive frame buffer 1 2 13 3 1 1 7 Line Stride Bits 15 0 are the stride between lines in bytes at the external address This value is adde...

Page 240: ...irst data transfer It should be set to the leftmost address fetch if the R to L field is not set in the descriptor If the R to L field is set then the address for the right most pixel should be specif...

Page 241: ...fer is turned into 2 or 4 line buffers depending on the container type For shared clients such as the ancillary data and the VIP port that use the memory only one can be active if the mode field is se...

Page 242: ...ts MReqPriority 2 0 Table 1 77 Priority Bit Fields Priority 11 Priority 10 Priority 9 Priority 11 9 Priority at EMIF 0 0 0 0 0 0 0 1 1 1 0 1 0 2 2 0 1 1 3 3 1 0 0 4 4 1 0 1 5 5 1 1 0 6 6 1 1 1 7 7 As...

Page 243: ...egister bit is set to 0 If this case is met when the channel is complete a descriptor that meets the inbound descriptor format will be written to the location specified by this field This allows for s...

Page 244: ...20 pixels Others Reserved 2 0 Max Height The maximum allowable lines per frame 0 Unlimited Frame Size 4 288 lines 5 576 lines 6 720 lines 7 1080 lines Others Reserved 1 2 13 3 1 6 2 1 Max Width Bits 6...

Page 245: ...the configuration takes place This ensures that all descriptors after a configuration descriptor in the list will occur after the desired configuration 1 2 13 3 2 1 Configuration Descriptor Header Wor...

Page 246: ...ed to bring the payload into the List Manager to allow for the payload to be sent to the destination 1 2 13 3 2 4 3 Class Bits 25 24 this field indicates the type of payload is associated with command...

Page 247: ...Tables 8 vip2 VIP1 Scaler Coefficient Tables 1 2 13 3 2 4 5 Payload Length Bits 15 0 this field indicates the size of the payload in words for the command This is 128 bit words The maximum number of...

Page 248: ..._STAT_SYNC bit specified or for an external event Sync on Channel 4h Wait for the channel specified to complete Change Client Interrupt 5h Change the interrupt event for a client interrupt but do not...

Page 249: ...to synchronize list 1 list 3 and list 4 then the source field would be 0x1a Word 0 Word 1 and Word 2 are reserved Table 1 92 Sync on List Field Descriptions Word 3 Bits Name Description 31 27 Packet...

Page 250: ...al to the Sync on Client Descriptor Word 0 is reserved Table 1 95 Change Client Interrupt Field Descriptions Word 1 Bits Name Description 31 16 PIXEL_COUNT Specify the pixel position on a line specifi...

Page 251: ...h the next section of the list This allows for the list to be dynamically adding new sections of a list The procedure to use a reload list descriptor as a mechanism to allow dynamic additions to a lis...

Page 252: ...scriptor is used if the clients set their frame source to LM FID The read clients will start transmitting data upon the FID signal inside the LM changing value This descriptor will cause the LM to tog...

Page 253: ...SC_4 422 444 444 422 VIP_PARSER1 CHR_DS0 RGB CHR_DS1 CSC_VIP0 SC_3 422 444 444 422 VIP_PARSER0 CHR_DS0 RGB CSC_HD0 CHR_US_P1 CHR_US_P0 420 2T 420 2T 420 2T 4 1 2 3 4 5 6 7 8 VPI Control Addresses 1 2...

Page 254: ...ta type 0x7 is used half the data fetched will be thrown out dei_2_chroma 8 dei_vid3_luma DEI Field Minus 2 420 Luma Data 4 YUV 0x1 0x2 0x7 If data type 0x7 is used half the data fetched will be throw...

Page 255: ...t A Channel 10 48 YUV 0x7 0x17 0x27 0x37 vip1_lo_y 2 vip1_mult_porta_src11 Video Input 1 Port A Channel 11 49 YUV 0x7 0x17 0x27 0x37 vip1_lo_y 2 vip1_mult_porta_src12 Video Input 1 Port A Channel 12 5...

Page 256: ...deo Input 1 Port A Ancillary Data Channel 6 76 OTHER 8 vip1_anc_a 2 vip1_mult_anca_src7 Video Input 1 Port A Ancillary Data Channel 7 77 OTHER 8 vip1_anc_a 2 vip1_mult_anca_src8 Video Input 1 Port A A...

Page 257: ...16 0x17 0x27 0x37 vip1_up_uv 1 vip1_portb_luma Video Input 1 Port B 420 Data Luma 104 YUV 0x1 0x2 0x7 0x17 0x27 0x37 vip1_lo_y 2 vip1_portb_chroma Video Input 1 Port B 420 Data Chroma 105 YUV 0x5 0x6...

Page 258: ...2 Port B Channel 7 131 YUV 0x7 0x17 0x27 0x37 vip2_lo_uv 20 vip2_mult_portb_src8 Video Input 2 Port B Channel 8 132 YUV 0x7 0x17 0x27 0x37 vip2_lo_uv 20 vip2_mult_portb_src9 Video Input 2 Port B Chan...

Page 259: ...ip2_mult_ancb_src3 Video Input 2 Port B Ancillary Data Channel 3 159 OTHER 8 vip2_anc_b 21 vip2_mult_ancb_src4 Video Input 2 Port B Ancillary Data Channel 4 160 OTHER 8 vip2_anc_b 21 vip2_mult_ancb_sr...

Page 260: ..._last_luma Noise Filter Previous Frame 420 Luma 181 YUV 0x2 nf_420_y_in 22 nf_last_chroma Noise Filter Previous Frame 420 Chroma 182 YUV 0x6 0x5 nf_420_uv_in 22 vbi_sd_venc SD Video Encoder VBI Data 1...

Page 261: ...11520 DEI_MQ_VID1 sc_in_luma scaler_luma 7680 TRANS_VID0 sc_out scaler_out 4096 MEM_TO_MEM comp_wrbk aux_in 4096 MEM_TO_MEM1 grpx1_data grpx1 4096 GRPX_BUF grpx2_data grpx2 4096 GRPX_BUF1 grpx3_data...

Page 262: ...rc3 vip2_mult_portb_src4 vip2_mult_portb_src5 vip2_mult_portb_src6 vip2_mult_portb_src7 vip2_mult_portb_src8 vip2_mult_portb_src9 vip2_mult_portb_src10 vip2_mult_portb_src11 vip2_mult_portb_src12 vip2...

Page 263: ...vip1_mult_anca_src13 vip1_mult_anca_src14 vip1_mult_anca_src15 0 VP_WR vip1_anc_b vip1_mult_ancb_src0 vip1_mult_ancb_src1 vip1_mult_ancb_src2 vip1_mult_ancb_src3 vip1_mult_ancb_src4 vip1_mult_ancb_sr...

Page 264: ...out Tiled Data Not Supported 4096 pip_wrbk Tiled Data Not Supported 4096 Virtual Video Buffer sc_in_chroma 1920 1920 Virtual Video Buffer with line buffer limitations TILED sc_in_luma 1920 4096 Virtua...

Page 265: ...p1 An unmasked channel interrupt for interrupt group 1 in channel register 0 has fired vpdma_int_channel_group2 An unmasked channel interrupt for interrupt group 2 in channel register 0 has fired vpdm...

Page 266: ...MA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer This will fire before the destination has received the data as it will have just been stored i...

Page 267: ...ill be fully empty at this point channel_nf_last_chroma channel_group5 The last write DMA transaction has completed for channel nf_last_chroma All data from the channel has been sent and received by t...

Page 268: ...w accept a new descriptor from the List Manager channel_vip1_mult_anca_ src0 channel_group2 The last write DMA transaction has completed for channel vip1_mult_anca_src0 All data from the channel has b...

Page 269: ...en setup for the client vip1_anc_a then the client will be fully empty at this point channel_vip1_mult_anca_ src9 channel_group2 The last write DMA transaction has completed for channel vip1_mult_anca...

Page 270: ...n setup for the client vip1_anc_b then the client will be fully empty at this point channel_vip1_mult_ancb_ src8 channel_group2 The last write DMA transaction has completed for channel vip1_mult_ancb_...

Page 271: ...been setup for the client vip1_lo_y then the client will be fully empty at this point channel_vip1_mult_porta _src7 channel_group1 The last write DMA transaction has completed for channel vip1_mult_po...

Page 272: ...xternal memory If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point channel_vip1_mult_portb _src6 channel_group1 The last write DMA transacti...

Page 273: ...r the client vip2_anc_a then the client will be fully empty at this point channel_vip2_mult_anca_ src13 channel_group4 The last write DMA transaction has completed for channel vip2_mult_anca_src13 All...

Page 274: ...been setup for the client vip2_anc_b then the client will be fully empty at this point channel_vip2_mult_ancb_ src12 channel_group5 The last write DMA transaction has completed for channel vip2_mult_...

Page 275: ...en setup for the client vip2_lo_y then the client will be fully empty at this point channel_vip2_mult_porta _src11 channel_group3 The last write DMA transaction has completed for channel vip2_mult_por...

Page 276: ...etup for the client vip2_lo_uv then the client will be fully empty at this point channel_vip2_mult_portb _src10 channel_group4 The last write DMA transaction has completed for channel vip2_mult_portb_...

Page 277: ...eived by the external memory If a new channel has not been setup for the client then the client will be fully empty at this point channel_vip2_porta_luma channel_group5 The last write DMA transaction...

Page 278: ...escriptor has been configured this will default to having received the End of Frame signal from the transmitting module client_grpx1_data client The client interface grpx1_data has reached its current...

Page 279: ...nfigured this will default to having sent the End of Frame signal to the receiving module client_sc_out client The client interface sc_out has reached its current configured interrupt event as specifi...

Page 280: ...eceived control descriptor for this client If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module client_vip2_lo_y clien...

Page 281: ...location of the list to the LIST_ADDRESS register and then writes the LIST_ATTRIBUTE register If the NUMBER in the LIST_ATTRIBUTE is not an active list then the List will be loaded and begin to execu...

Page 282: ...he same settings for the chroma assuming that the data type is 422 The line buffer mode is set by the CSTAT register for the client This value is not shadowed and must be set before the descriptor is...

Page 283: ...figuration AF Word 6 Bit 10 The region should be passed through the scaler to Anti flicker the data Stencil Word 6 Bit 11 The region should use the stencil client applied to this data A separate data...

Page 284: ...30 Format of the source image 0 Progressive 1 Interlaced Soft Reset Payload Word 3 Bit 31 Software reset of GRPX data pipeline Table 1 112 Frame with Resizer Configuration Descriptor Format Attribute...

Page 285: ...yload Word 18 Bits 9 0 Coefficient for Horizontal TAP 3 Phase 4 coefh3_p5 Payload Word 18 Bits 25 16 Coefficient for Horizontal TAP 3 Phase 5 coefh3_p6 Payload Word 19 Bits 9 0 Coefficient for Horizon...

Page 286: ...rtical TAP 2 Phase 5 coefv2_p6 Payload Word 36 Bits 9 0 Coefficient for Vertical TAP 2 Phase 6 coefv2_p7 Payload Word 36 Bits 25 16 Coefficient for Vertical TAP 2 Phase 7 coefv3_p0 Payload Word 37 Bit...

Page 287: ...deo Processing Subsystem HDVPSS 1 2 13 5 1 5 3 Example Graphics List An example of how a graphics port can be configured will be shown using an example of three frames with the frame size changing In...

Page 288: ...or region 2 2 Data transfer descriptor Sets up the stencil data for region 1 Size is the pre scaled size of region 1 2 Data transfer descriptor Sets up the data for region 1 2 Data transfer descriptor...

Page 289: ...space The YUV data can be type is for YUV data and it can support both interleaved data where Luma and Chroma are in the same data buffer or it can support co planar data where the Luma and Chroma ar...

Page 290: ...d for a co planar 4 2 2 data In this mode the data is assumed to be a single byte with each pixel is packed in a line If a 2D transfer of the data is used the VPDMA will assume this data type is store...

Page 291: ...2012 Revised June 2016 Submit Documentation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS 1 2 13 6 1 4 C 4 4 4 Data Type 4 The C 4 4 4 d...

Page 292: ...ype 5 The C 4 2 2 data type is used for co planar 4 2 2 data It is expected to be packed Cb in the lower byte and Cr in the upper byte in 16 bit words for each pixel If a 2D transfer of the data is us...

Page 293: ...ion Video Processing Subsystem HDVPSS 1 2 13 6 1 7 YC 4 2 2 Data Type 7 The YC 4 2 2 data type is used for interleaved 4 2 2 data It is expected to be packed with Y0 in the lowest byte followed by Cb...

Page 294: ...ntation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS 1 2 13 6 1 8 YC 4 4 4 Data Type 8 The YC 4 4 4 data type is used for interleaved 4...

Page 295: ...n Video Processing Subsystem HDVPSS 1 2 13 6 1 9 CY 4 2 2 Data Type 23h The CY 4 2 2 data type is used for interleaved 4 2 2 data It is expected to be packed with Cb in the lowest byte followed by Y0...

Page 296: ...Incorporated High Definition Video Processing Subsystem HDVPSS 1 2 13 6 1 10 Cb 4 4 4 Data Type 14h The Cb 4 4 4 data type is used for a co planar 4 4 4 data It is expected to be packed Cb in the lowe...

Page 297: ...packed Cb in the lower byte and Cr in the upper byte in 16 bit words for each pixel If a 2D transfer of the data is used the VPDMA will assume this data type is stored in a 16 bit container as descri...

Page 298: ...the lowest byte followed by Cr followed by Y1 finally Cb in the upper most byte The transfer counts each YC pair in a 16 bit word as a pixel but the number of pixels should be even If a 2D transfer o...

Page 299: ...to provide a full 32 bit RGBA data stream to the client In all modes the client is provided RGBA 8888 data The lower bits if not provided by the data stream are a replication of the lower bit of the d...

Page 300: ...GB pixel with 16 bits of data for each pixel The 16 bits of data uses the lower 5 bits for blue data the next 5 bits for green data the next 5 bits for red data and the upper most bit for the blend va...

Page 301: ...ARGB pixel with 16 bits of data for each pixel The 16 bits of data uses the lowest most bit for the blend value to use 0 or 0xff the next 5 bits for blue data the next 5 bits for green data the next...

Page 302: ...RGB pixel with 24 bits of data for each pixel The 24 bits of data uses the lowest 6 bits for the blend value the next 6 bits for blue data the next 6 bits for green data and the upper most 6 bits for...

Page 303: ...orporated High Definition Video Processing Subsystem HDVPSS 1 2 13 6 2 8 ARGB32 8888 Data Type 7 In ARGB32 8888 mode each pixel is a single ARGB pixel with 32 bits of data for each pixel The 32 bitsof...

Page 304: ...s Incorporated High Definition Video Processing Subsystem HDVPSS 1 2 13 6 2 9 RGBA24 6666 Data Type 8 In RGBA24 6666 mode each pixel is a single RGBA pixel with 24 bits of data for each pixel The 24 b...

Page 305: ...ncorporated High Definition Video Processing Subsystem HDVPSS 1 2 13 6 2 10 RGBA32 8888 Data Type 9 In RGBA32 8888 mode each pixel is a single ARGB pixel with 32 bits of data for each pixel The 32 bit...

Page 306: ...Definition Video Processing Subsystem HDVPSS 1 2 13 6 2 11 Bitmap 8 Data Type 20h In Bitmap 8 data each pixel is an 8 bit value that is used as an address into a 256 32 memory that gives the final RGB...

Page 307: ...13 Bitmap 4 Upper Data Type 23h In Bitmap 4 Upper data each pixel is an 4 bit value that is used as the lower 4 bits of address into a 256 32 memory that gives the final RGBA32 8888 data value The upp...

Page 308: ...Offset1 Data Type 25h In Bitmap 2 Offset1 data each pixel is a 2 bit value that is used as the lower 2 bits of address into a 256 32 memory that gives the final RGBA32 8888 data value The upper 2 bits...

Page 309: ...Offset3 Data Type 27h In Bitmap 2 Offset3 data each pixel is a 2 bit value that is used as the lower 2 bits of address into a 256 32 memory that gives the final RGBA32 8888 data value The upper 2 bit...

Page 310: ...1 Offset1 Data Type 29h In Bitmap 1 Offset1 data each pixel is an 1 bit value that is used as the lower bit of address into a 256 32 memory that gives the final RGBA32 8888 data value The upper 3 bits...

Page 311: ...tmap 1 Offset3 Data Type 2Bh In Bitmap 1 Offset3 data each pixel is an 1 bit value that is used as the lower bit of address into a 256 32 memory that gives the final RGBA32 8888 data value The upper 3...

Page 312: ...1 Offset5 Data Type 2Dh In Bitmap 1 Offset5 data each pixel is an 1 bit value that is used as the lower bit of address into a 256 32 memory that gives the final RGBA32 8888 data value The upper 3 bits...

Page 313: ...lue The upper 3 bits in this case are tied to 3 b111 Bits 1 4 are tied to 0 Figure 1 210 Bitmap 1 Offset7 Data Type 2Fh 1 2 13 6 3 Miscellaneous Data Type The Miscellaneous channel type is for any dat...

Page 314: ...address of CSC_csc02 0x4810 0000 Base Address of HDVPSS 0x0000 0C00 Instance Offset Address CSC_HD1 from Table 1 115 0x0000 0008 Register Offset Address CSC_csc02 from corresponding instance register...

Page 315: ...s controlled by registers VIP1 Submodule VIP1 is controlled by registers VIP2 Submodule GRPX0 is controlled by registers GRPX1 Submodule GRPX1 is controlled by registers GRPX2 Submodule GRPX2 is contr...

Page 316: ...considered as reserved locations and the register contents should not be modified Table 1 116 CHR_US REGISTERS Offset Acronym Register Name Section 4h CHR_US_reg0 Upsampling Coeffs Section 1 3 1 1 8h...

Page 317: ...5 24 ANCHOR_FID0_C0 R W 0h 23 22 21 20 19 18 17 16 ANCHOR_FID0_C0 CFG_MODE R W 0h R W 0h 15 14 13 12 11 10 9 8 ANCHOR_FID0_C1 R W 0h 7 6 5 4 3 2 1 0 ANCHOR_FID0_C1 Reserved R W 0h R 0h LEGEND R W Read...

Page 318: ...27 26 25 24 ANCHOR_FID0_C2 R W 0h 23 22 21 20 19 18 17 16 ANCHOR_FID0_C2 Reserved R W 0h R 0h 15 14 13 12 11 10 9 8 ANCHOR_FID0_C3 R W 0h 7 6 5 4 3 2 1 0 ANCHOR_FID0_C3 Reserved R W 0h R 0h LEGEND R...

Page 319: ...25 24 INTERP_FID0_C0 R W 0h 23 22 21 20 19 18 17 16 INTERP_FID0_C0 Reserved R W 0h R 0h 15 14 13 12 11 10 9 8 INTERP_FID0_C1 R W 0h 7 6 5 4 3 2 1 0 INTERP_FID0_C1 Reserved R W 0h R 0h LEGEND R W Read...

Page 320: ...25 24 INTERP_FID0_C2 R W 0h 23 22 21 20 19 18 17 16 INTERP_FID0_C2 Reserved R W 0h R 0h 15 14 13 12 11 10 9 8 INTERP_FID0_C3 R W 0h 7 6 5 4 3 2 1 0 INTERP_FID0_C3 Reserved R W 0h R 0h LEGEND R W Read...

Page 321: ...27 26 25 24 ANCHOR_FID1_C0 R W 0h 23 22 21 20 19 18 17 16 ANCHOR_FID1_C0 Reserved R W 0h R 0h 15 14 13 12 11 10 9 8 ANCHOR_FID1_C1 R W 0h 7 6 5 4 3 2 1 0 ANCHOR_FID1_C1 Reserved R W 0h R 0h LEGEND R...

Page 322: ...27 26 25 24 ANCHOR_FID1_C2 R W 0h 23 22 21 20 19 18 17 16 ANCHOR_FID1_C2 Reserved R W 0h R 0h 15 14 13 12 11 10 9 8 ANCHOR_FID1_C3 R W 0h 7 6 5 4 3 2 1 0 ANCHOR_FID1_C3 Reserved R W 0h R 0h LEGEND R...

Page 323: ...25 24 INTERP_FID1_C0 R W 0h 23 22 21 20 19 18 17 16 INTERP_FID1_C0 Reserved R W 0h R 0h 15 14 13 12 11 10 9 8 INTERP_FID1_C1 R W 0h 7 6 5 4 3 2 1 0 INTERP_FID1_C1 Reserved R W 0h R 0h LEGEND R W Read...

Page 324: ...25 24 INTERP_FID1_C2 R W 0h 23 22 21 20 19 18 17 16 INTERP_FID1_C2 Reserved R W 0h R 0h 15 14 13 12 11 10 9 8 INTERP_FID1_C3 R W 0h 7 6 5 4 3 2 1 0 INTERP_FID1_C3 Reserved R W 0h R 0h LEGEND R W Read...

Page 325: ...ffset Acronym Register Name Section 0h CIG_reg0 CIG Mode Reg Section 1 3 2 1 4h CIG_reg1 CIG Display Config Reg Section 1 3 2 2 8h CIG_reg2 CIG HDMI Transparency Config Reg Section 1 3 2 3 Ch CIG_reg3...

Page 326: ...ue after reset Table 1 126 CIG_reg0 Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h Reserved 7 PIP_P2I_EN R W 0h Enable Output Interlacing for PIP output 0 Disabled 1 E...

Page 327: ...g Figure 1 220 CIG_reg1 Register 31 30 29 28 27 26 25 24 Reserved DISP_W R 0h R W 0h 23 22 21 20 19 18 17 16 DISP_W R W 0h 15 14 13 12 11 10 9 8 Reserved DISP_H R 0h R W 0h 7 6 5 4 3 2 1 0 DISP_H R W...

Page 328: ...3 2 1 0 BL_LEVEL BL_ENABLE TR_MODE_MASK TR_ENABLE R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 128 CIG_reg2 Register Field Des...

Page 329: ...Figure 1 222 CIG_reg3 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 TR_COLOR R W 0h 15 14 13 12 11 10 9 8 TR_COLOR R W 0h 7 6 5 4 3 2 1 0 TR_COLOR R W 0h LEGEND R W Read Write...

Page 330: ...4 3 2 1 0 BL_LEVEL BL_ENABLE TR_MODE_MASK TR_ENABLE R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 130 CIG_reg4 Register Field D...

Page 331: ...r Figure 1 224 CIG_reg5 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 TR_COLOR R W 0h 15 14 13 12 11 10 9 8 TR_COLOR R W 0h 7 6 5 4 3 2 1 0 TR_COLOR R W 0h LEGEND R W Read Wri...

Page 332: ...5 CIG_reg6 Register 31 30 29 28 27 26 25 24 Reserved PIP_DISP_W R 0h R W 0h 23 22 21 20 19 18 17 16 PIP_DISP_W R W 0h 15 14 13 12 11 10 9 8 Reserved PIP_DISP_H R 0h R W 0h 7 6 5 4 3 2 1 0 PIP_DISP_H R...

Page 333: ...ition Config Reg Figure 1 226 CIG_reg7 Register 31 30 29 28 27 26 25 24 Reserved PIP_X R 0h R W 0h 23 22 21 20 19 18 17 16 PIP_X R W 0h 15 14 13 12 11 10 9 8 Reserved PIP_Y R 0h R W 0h 7 6 5 4 3 2 1 0...

Page 334: ...r 31 30 29 28 27 26 25 24 Reserved PIP_W R 0h R W 0h 23 22 21 20 19 18 17 16 PIP_W R W 0h 15 14 13 12 11 10 9 8 Reserved PIP_H R 0h R W 0h 7 6 5 4 3 2 1 0 PIP_H R W 0h LEGEND R W Read Write R Read onl...

Page 335: ...4 3 2 1 0 BL_LEVEL BL_ENABLE TR_MODE_MASK TR_ENABLE R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 135 CIG_reg9 Register Field De...

Page 336: ...Figure 1 229 CIG_reg10 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 TR_COLOR R W 0h 15 14 13 12 11 10 9 8 TR_COLOR R W 0h 7 6 5 4 3 2 1 0 TR_COLOR R W 0h LEGEND R W Read Wri...

Page 337: ...le 1 137 should be considered as reserved locations and the register contents should not be modified Table 1 137 COMP REGISTERS Offset Acronym Register Name Section 0h COMP_status Compositor Status Se...

Page 338: ...R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 138 COMP_status Register Field Descriptions Bit Field Type Reset Description 30 26 Reserved...

Page 339: ...R 0h Reserved 16 FB_SEL R W 0h Feedback data selection 0 select data from video alpha blending 1 select data from final alpha blending 15 14 G2_ORDER R W 3h Graphic2 layer display order when g_order 1...

Page 340: ...t data from video alpha blending 1 select data from final alpha blending 15 14 G2_ORDER R W 3h Graphic2 layer display order when g_order 1 From low to high 00 01 10 and 11 13 12 G1_ORDER R W 2h Graphi...

Page 341: ...elect data from video alpha blending 1 select data from final alpha blending 15 14 G2_ORDER R W 3h Graphic2 layer display order when g_order 1 From low to high 00 01 10 and 11 13 12 G1_ORDER R W 2h Gr...

Page 342: ...Descriptions Bit Field Type Reset Description 31 17 Reserved R 0h Reserved 16 FB_SEL R W 0h Feedback data selection 0 select data from video alpha blending 1 select data from final alpha blending 15 1...

Page 343: ...Register 31 30 29 28 27 26 25 24 Reserved BACK_CLR R 0h R W 0h 23 22 21 20 19 18 17 16 BACK_CLR R W 0h 15 14 13 12 11 10 9 8 BACK_CLR R W 0h 7 6 5 4 3 2 1 0 BACK_CLR R W 0h LEGEND R W Read Write R Rea...

Page 344: ...in Table 1 144 should be considered as reserved locations and the register contents should not be modified Table 1 144 CSC REGISTERS Offset Acronym Register Name Section 0h CSC_csc00 Color Space Conv...

Page 345: ...ons Bit Field Type Reset Description 31 29 Reserved R 0h Reserved 28 16 B0 R W 0h Coefficients of color space converter This coefficient is a real number in the range of 4 to 4 represent in Q3 10 form...

Page 346: ...Reserved C0 R 0h R W 0h 7 6 5 4 3 2 1 0 C0 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 146 CSC_csc01 Register Field Descriptions Bit Field Type Re...

Page 347: ...Reserved B1 R 0h R W 0h 7 6 5 4 3 2 1 0 B1 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 147 CSC_csc02 Register Field Descriptions Bit Field Type Re...

Page 348: ...Reserved A2 R 0h R W 0h 7 6 5 4 3 2 1 0 A2 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 148 CSC_csc03 Register Field Descriptions Bit Field Type Re...

Page 349: ...1toCl Write 1 to clear bit n value after reset Table 1 149 CSC_csc04 Register Field Descriptions Bit Field Type Reset Description 31 28 Reserved R 0h Reserved 27 16 D0 R W 0h Coefficients of color spa...

Page 350: ...0 D1 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 150 CSC_csc05 Register Field Descriptions Bit Field Type Reset Description 31 29 Reserved R 0h Res...

Page 351: ...r Bypass Register Section 1 3 5 2 8h dei_reg2 MDT Spatial Frequency Threshold Register Section 1 3 5 3 Ch dei_reg3 EDI Configuration Control Section 1 3 5 4 10h dei_reg4 EDI Lookup Table Register 0 Se...

Page 352: ...0h R W 1E0h 23 22 21 20 19 18 17 16 HEIGHT R W 1E0h 15 14 13 12 11 10 9 8 Reserved WIDTH R 0h R W 2D0h 7 6 5 4 3 2 1 0 WIDTH R W 2D0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n va...

Page 353: ...served R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved MDT_SPATMAX_BYP ASS MDT_TEMPMAX_BY PASS R 0h R W 0h R W 0h LEGEND R W Read Write R Read o...

Page 354: ...old leads to more robustness to noise but with the potential of introducing ghosting effect Note that this threshold is used for motion values for EDI only and it is in addition mdt_mv_cor_thr 27 24 M...

Page 355: ...THR R W 18h Lower threshold used for correlation along detected edge 15 8 EDI_CHROMA3D_COR_ THR R W 10h Correlation threshold used in 3D processing for chroma Because the motion values used for chroma...

Page 356: ...20 19 18 17 16 Reserved EDI_LUT2 R 0h R W 4h 15 14 13 12 11 10 9 8 Reserved EDI_LUT1 R 0h R W 2h 7 6 5 4 3 2 1 0 Reserved EDI_LUT0 R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear...

Page 357: ...T7 R 0h R W 10h 23 22 21 20 19 18 17 16 Reserved EDI_LUT6 R 0h R W 10h 15 14 13 12 11 10 9 8 Reserved EDI_LUT5 R 0h R W 10h 7 6 5 4 3 2 1 0 Reserved EDI_LUT4 R 0h R W Ch LEGEND R W Read Write R Read o...

Page 358: ...R 0h R W 10h 23 22 21 20 19 18 17 16 Reserved EDI_LUT10 R 0h R W 10h 15 14 13 12 11 10 9 8 Reserved EDI_LUT9 R 0h R W 10h 7 6 5 4 3 2 1 0 Reserved EDI_LUT8 R 0h R W 10h LEGEND R W Read Write R Read on...

Page 359: ...h R W 10h 23 22 21 20 19 18 17 16 Reserved EDI_LUT14 R 0h R W 10h 15 14 13 12 11 10 9 8 Reserved EDI_LUT13 R 0h R W 10h 7 6 5 4 3 2 1 0 Reserved EDI_LUT12 R 0h R W 10h LEGEND R W Read Write R Read onl...

Page 360: ...D_WINDOW_MAXX R W 1h R 0h R W 2CFh 23 22 21 20 19 18 17 16 FMD_WINDOW_MAXX R W 2CFh 15 14 13 12 11 10 9 8 Reserved FMD_WINDOW_MINX R 0h R W 0h 7 6 5 4 3 2 1 0 FMD_WINDOW_MINX R W 0h LEGEND R W Read Wr...

Page 361: ...27 26 25 24 Reserved FMD_WINDOW_MAXY R 0h R W EFh 23 22 21 20 19 18 17 16 FMD_WINDOW_MAXY R W EFh 15 14 13 12 11 10 9 8 Reserved FMD_WINDOW_MINY R 0h R W 0h 7 6 5 4 3 2 1 0 FMD_WINDOW_MINY R W 0h LEGE...

Page 362: ...difference of two consecutive lines from the same field so there is one line in between if two fields are merged into one progressive frame is compared with this threshold Decreasing this threshold le...

Page 363: ...R R 0h R W 2004h 15 14 13 12 11 10 9 8 FMD_CAF_THR R W 2004h 7 6 5 4 3 2 1 0 FMD_CAF_THR R W 2004h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 163 dei_reg...

Page 364: ...ved FMD_CAF R 0h R 0h 15 14 13 12 11 10 9 8 FMD_CAF R 0h 7 6 5 4 3 2 1 0 FMD_CAF R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 164 dei_reg12 Register F...

Page 365: ...gister 1 Figure 1 255 dei_reg13 Register 31 30 29 28 27 26 25 24 Reserved FMD_FIELD_DIFF R 0h R 0h 23 22 21 20 19 18 17 16 FMD_FIELD_DIFF R 0h 15 14 13 12 11 10 9 8 FMD_FIELD_DIFF R 0h 7 6 5 4 3 2 1 0...

Page 366: ...MD Status Register 2 Figure 1 256 dei_reg14 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved FMD_FRAME_DIFF R 0h R 0h 15 14 13 12 11 10 9 8 FMD_FRAME_DIFF R 0h 7 6 5 4 3...

Page 367: ...2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS 1 3 6 GRPX Registers The graphics module GRPX is configured using VPDMA frame and region descriptors Please...

Page 368: ...na_clr0 Interrupt1 Enable Clear Register 0 Section 1 3 7 17 5Ch intc_intr1_ena_clr1 Interrupt1 Enable Clear Register 1 Section 1 3 7 18 60h intc_intr2_status_raw0 Interrupt2 Raw Register 0 Section 1 3...

Page 369: ...umentation Feedback Copyright 2012 2016 Texas Instruments Incorporated High Definition Video Processing Subsystem HDVPSS Table 1 167 INTC_CLKC_CONTROL REGISTERS continued Offset Acronym Register Name...

Page 370: ...23 22 21 20 19 18 17 16 FUNC R F00h 15 14 13 12 11 10 9 8 RTL MAJOR R 5h R 0h 7 6 5 4 3 2 1 0 CUSTOM MINOR R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset T...

Page 371: ...58 sysconfig Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved STANDBYMODE IDLEMODE Reserved R 0h R W 2h...

Page 372: ...0 has no effect 30 DVO2_INT2_RAW R W 0h DVO2 Interrupt2 Status Read indicates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 29 DVO2_INT1_RAW R W 0h DVO2 Interrupt1...

Page 373: ...cates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 7 VPDMA_INT0_LIST3_NO TIFY_RAW R W 0h VPDMA INT0 List3 Complete Status Read indicates raw status 0 inactive 1 act...

Page 374: ...riting 0 has no effect 24 VIP2_CHR_DS_1_UV_ER R_INT_RAW R W 0h VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has...

Page 375: ...VPDMA_INT0_CHANNEL _GROUP4_RAW R W 0h VPDMA INT0 Channel Group4 Status Read indicates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 3 VPDMA_INT0_CHANNEL _GROUP3_RAW...

Page 376: ...1 to clear bit n value after reset Table 1 172 intc_intr0_status_ena0 Register Field Descriptions Bit Field Type Reset Description 31 SDVENC_INT_ENA R W 0h SD_VENC Interrupt Enabled Status Read indic...

Page 377: ...g 1 will set interrupt enabled Writing 0 has no effect 9 VPDMA_INT0_LIST4_NO TIFY_ENA R W 0h VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will...

Page 378: ...ll clear interrupt Writing 0 has no effect 24 VIP2_CHR_DS_1_UV_ER R_INT_ENA R W 0h VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 inactive 1 active Writing...

Page 379: ...tatus 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 4 VPDMA_INT0_CHANNEL _GROUP4_ENA R W 0h VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status 0 inactive 1 acti...

Page 380: ...eset Table 1 174 intc_intr0_ena_set0 Register Field Descriptions Bit Field Type Reset Description 31 SDVENC_INT_ENA_SET R W 0h SD_VENC Interrupt Enable Set Read indicates interrupt enable 0 disabled 1...

Page 381: ...0h VPDMA INT0 List4 Notify Enable Set Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will set interrupt enabled Writing 0 has no effect 8 VPDMA_INT0_LIST4_CO MPLETE_ENA_SET R W 0h VPDM...

Page 382: ...R_INT_ENA_SET R W 0h VIP2 Chroma Downsampler 1 UV Error Enable Set Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will set interrupt enabled Writing 0 has no effect 23 VIP1_CHR_DS_2_U...

Page 383: ...h VPDMA INT0 Channel Group4 Enable Set Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will set interrupt enabled Writing 0 has no effect 3 VPDMA_INT0_CHANNEL _GROUP3_ENA_SET R W 0h VPD...

Page 384: ...tc_intr0_ena_clr0 Register Field Descriptions Bit Field Type Reset Description 31 SDVENC_INT_ENA_CLR R W 0h SD_VENC Interrupt Enable Clear Read indicates interrupt enable 0 disabled 1 enabled Writing...

Page 385: ...MA INT0 List4 Notify Enable Clear Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will clear interrupt enabled Writing 0 has no effect 8 VPDMA_INT0_LIST4_CO MPLETE_ENA_CLR R W 0h VPDMA...

Page 386: ...Writing 1 will clear interrupt enabled Writing 0 has no effect 24 VIP2_CHR_DS_1_UV_ER R_INT_ENA_CLR R W 0h VIP2 Chroma Downsampler 1 UV Error Enable Clear Read indicates interrupt enable 0 disabled 1...

Page 387: ...will clear interrupt enabled Writing 0 has no effect 4 VPDMA_INT0_CHANNEL _GROUP4_ENA_CLR R W 0h VPDMA INT0 Channel Group4 Enable Clear Read indicates interrupt enable 0 disabled 1 enabled Writing 1 w...

Page 388: ...0 has no effect 30 DVO2_INT2_RAW R W 0h DVO2 Interrupt2 Status Read indicates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 29 DVO2_INT1_RAW R W 0h DVO2 Interrupt1...

Page 389: ...cates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 7 VPDMA_INT1_LIST3_NO TIFY_RAW R W 0h VPDMA INT0 List3 Complete Status Read indicates raw status 0 inactive 1 act...

Page 390: ...riting 0 has no effect 24 VIP2_CHR_DS_1_UV_ER R_INT_RAW R W 0h VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has...

Page 391: ...VPDMA_INT1_CHANNEL _GROUP4_RAW R W 0h VPDMA INT0 Channel Group4 Status Read indicates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 3 VPDMA_INT1_CHANNEL _GROUP3_RAW...

Page 392: ...e 1 to clear bit n value after reset Table 1 180 intc_intr1_status_ena0 Register Field Descriptions Bit Field Type Reset Description 31 SDVENC_INT_ENA R W 0h SD_VENC Interrupt Enabled Status Read indi...

Page 393: ...g 1 will set interrupt enabled Writing 0 has no effect 9 VPDMA_INT1_LIST4_NO TIFY_ENA R W 0h VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will...

Page 394: ...ll clear interrupt Writing 0 has no effect 24 VIP2_CHR_DS_1_UV_ER R_INT_ENA R W 0h VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 inactive 1 active Writing...

Page 395: ...tatus 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 4 VPDMA_INT1_CHANNEL _GROUP4_ENA R W 0h VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status 0 inactive 1 acti...

Page 396: ...reset Table 1 182 intc_intr1_ena_set0 Register Field Descriptions Bit Field Type Reset Description 31 SDVENC_INT_ENA_SET R W 0h SD_VENC Interrupt Enable Set Read indicates interrupt enable 0 disabled...

Page 397: ...0h VPDMA INT0 List4 Notify Enable Set Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will set interrupt enabled Writing 0 has no effect 8 VPDMA_INT1_LIST4_CO MPLETE_ENA_SET R W 0h VPDM...

Page 398: ...R R_INT_ENA_SET R W 0h VIP2 Chroma Downsampler 1 UV Error Enable Set Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will set interrupt enabled Writing 0 has no effect 23 VIP1_CHR_DS_2_...

Page 399: ...h VPDMA INT0 Channel Group4 Enable Set Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will set interrupt enabled Writing 0 has no effect 3 VPDMA_INT1_CHANNEL _GROUP3_ENA_SET R W 0h VPD...

Page 400: ...ntc_intr1_ena_clr0 Register Field Descriptions Bit Field Type Reset Description 31 SDVENC_INT_ENA_CLR R W 0h SD_VENC Interrupt Enable Clear Read indicates interrupt enable 0 disabled 1 enabled Writing...

Page 401: ...MA INT0 List4 Notify Enable Clear Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will clear interrupt enabled Writing 0 has no effect 8 VPDMA_INT1_LIST4_CO MPLETE_ENA_CLR R W 0h VPDMA...

Page 402: ...Writing 1 will clear interrupt enabled Writing 0 has no effect 24 VIP2_CHR_DS_1_UV_ER R_INT_ENA_CLR R W 0h VIP2 Chroma Downsampler 1 UV Error Enable Clear Read indicates interrupt enable 0 disabled 1...

Page 403: ...will clear interrupt enabled Writing 0 has no effect 4 VPDMA_INT1_CHANNEL _GROUP4_ENA_CLR R W 0h VPDMA INT0 Channel Group4 Enable Clear Read indicates interrupt enable 0 disabled 1 enabled Writing 1 w...

Page 404: ...0 has no effect 30 DVO2_INT2_RAW R W 0h DVO2 Interrupt2 Status Read indicates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 29 DVO2_INT1_RAW R W 0h DVO2 Interrupt1...

Page 405: ...cates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 7 VPDMA_INT2_LIST3_NO TIFY_RAW R W 0h VPDMA INT0 List3 Complete Status Read indicates raw status 0 inactive 1 act...

Page 406: ...riting 0 has no effect 24 VIP2_CHR_DS_1_UV_ER R_INT_RAW R W 0h VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has...

Page 407: ...VPDMA_INT2_CHANNEL _GROUP4_RAW R W 0h VPDMA INT0 Channel Group4 Status Read indicates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 3 VPDMA_INT2_CHANNEL _GROUP3_RAW...

Page 408: ...e 1 to clear bit n value after reset Table 1 188 intc_intr2_status_ena0 Register Field Descriptions Bit Field Type Reset Description 31 SDVENC_INT_ENA R W 0h SD_VENC Interrupt Enabled Status Read indi...

Page 409: ...g 1 will set interrupt enabled Writing 0 has no effect 9 VPDMA_INT2_LIST4_NO TIFY_ENA R W 0h VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will...

Page 410: ...ll clear interrupt Writing 0 has no effect 24 VIP2_CHR_DS_1_UV_ER R_INT_ENA R W 0h VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 inactive 1 active Writing...

Page 411: ...tatus 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 4 VPDMA_INT2_CHANNEL _GROUP4_ENA R W 0h VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status 0 inactive 1 acti...

Page 412: ...reset Table 1 190 intc_intr2_ena_set0 Register Field Descriptions Bit Field Type Reset Description 31 SDVENC_INT_ENA_SET R W 0h SD_VENC Interrupt Enable Set Read indicates interrupt enable 0 disabled...

Page 413: ...0h VPDMA INT0 List4 Notify Enable Set Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will set interrupt enabled Writing 0 has no effect 8 VPDMA_INT2_LIST4_CO MPLETE_ENA_SET R W 0h VPDM...

Page 414: ...R R_INT_ENA_SET R W 0h VIP2 Chroma Downsampler 1 UV Error Enable Set Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will set interrupt enabled Writing 0 has no effect 23 VIP1_CHR_DS_2_...

Page 415: ...h VPDMA INT0 Channel Group4 Enable Set Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will set interrupt enabled Writing 0 has no effect 3 VPDMA_INT2_CHANNEL _GROUP3_ENA_SET R W 0h VPD...

Page 416: ...ntc_intr2_ena_clr0 Register Field Descriptions Bit Field Type Reset Description 31 SDVENC_INT_ENA_CLR R W 0h SD_VENC Interrupt Enable Clear Read indicates interrupt enable 0 disabled 1 enabled Writing...

Page 417: ...MA INT0 List4 Notify Enable Clear Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will clear interrupt enabled Writing 0 has no effect 8 VPDMA_INT2_LIST4_CO MPLETE_ENA_CLR R W 0h VPDMA...

Page 418: ...Writing 1 will clear interrupt enabled Writing 0 has no effect 24 VIP2_CHR_DS_1_UV_ER R_INT_ENA_CLR R W 0h VIP2 Chroma Downsampler 1 UV Error Enable Clear Read indicates interrupt enable 0 disabled 1...

Page 419: ...will clear interrupt enabled Writing 0 has no effect 4 VPDMA_INT2_CHANNEL _GROUP4_ENA_CLR R W 0h VPDMA INT0 Channel Group4 Enable Clear Read indicates interrupt enable 0 disabled 1 enabled Writing 1 w...

Page 420: ...0 has no effect 30 DVO2_INT2_RAW R W 0h DVO2 Interrupt2 Status Read indicates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 29 DVO2_INT1_RAW R W 0h DVO2 Interrupt1...

Page 421: ...cates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 7 VPDMA_INT3_LIST3_NO TIFY_RAW R W 0h VPDMA INT0 List3 Complete Status Read indicates raw status 0 inactive 1 act...

Page 422: ...riting 0 has no effect 24 VIP2_CHR_DS_1_UV_ER R_INT_RAW R W 0h VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has...

Page 423: ...VPDMA_INT3_CHANNEL _GROUP4_RAW R W 0h VPDMA INT0 Channel Group4 Status Read indicates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 3 VPDMA_INT3_CHANNEL _GROUP3_RAW...

Page 424: ...e 1 to clear bit n value after reset Table 1 196 intc_intr3_status_ena0 Register Field Descriptions Bit Field Type Reset Description 31 SDVENC_INT_ENA R W 0h SD_VENC Interrupt Enabled Status Read indi...

Page 425: ...g 1 will set interrupt enabled Writing 0 has no effect 9 VPDMA_INT3_LIST4_NO TIFY_ENA R W 0h VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will...

Page 426: ...ll clear interrupt Writing 0 has no effect 24 VIP2_CHR_DS_1_UV_ER R_INT_ENA R W 0h VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 inactive 1 active Writing...

Page 427: ...tatus 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 4 VPDMA_INT3_CHANNEL _GROUP4_ENA R W 0h VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status 0 inactive 1 acti...

Page 428: ...reset Table 1 198 intc_intr3_ena_set0 Register Field Descriptions Bit Field Type Reset Description 31 SDVENC_INT_ENA_SET R W 0h SD_VENC Interrupt Enable Set Read indicates interrupt enable 0 disabled...

Page 429: ...0h VPDMA INT0 List4 Notify Enable Set Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will set interrupt enabled Writing 0 has no effect 8 VPDMA_INT3_LIST4_CO MPLETE_ENA_SET R W 0h VPDM...

Page 430: ...R R_INT_ENA_SET R W 0h VIP2 Chroma Downsampler 1 UV Error Enable Set Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will set interrupt enabled Writing 0 has no effect 23 VIP1_CHR_DS_2_...

Page 431: ...h VPDMA INT0 Channel Group4 Enable Set Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will set interrupt enabled Writing 0 has no effect 3 VPDMA_INT3_CHANNEL _GROUP3_ENA_SET R W 0h VPD...

Page 432: ...ntc_intr3_ena_clr0 Register Field Descriptions Bit Field Type Reset Description 31 SDVENC_INT_ENA_CLR R W 0h SD_VENC Interrupt Enable Clear Read indicates interrupt enable 0 disabled 1 enabled Writing...

Page 433: ...MA INT0 List4 Notify Enable Clear Read indicates interrupt enable 0 disabled 1 enabled Writing 1 will clear interrupt enabled Writing 0 has no effect 8 VPDMA_INT3_LIST4_CO MPLETE_ENA_CLR R W 0h VPDMA...

Page 434: ...Writing 1 will clear interrupt enabled Writing 0 has no effect 24 VIP2_CHR_DS_1_UV_ER R_INT_ENA_CLR R W 0h VIP2 Chroma Downsampler 1 UV Error Enable Clear Read indicates interrupt enable 0 disabled 1...

Page 435: ...will clear interrupt enabled Writing 0 has no effect 4 VPDMA_INT3_CHANNEL _GROUP4_ENA_CLR R W 0h VPDMA INT0 Channel Group4 Enable Clear Read indicates interrupt enable 0 disabled 1 enabled Writing 1 w...

Page 436: ...ster 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EOI_VECTOR R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 2...

Page 437: ...e 1 Clock Enabled 0 Clock Disabled 23 18 Reserved R 0h 17 VIP2_DP_EN R W 0h Video Input Port 2 Data Path Clock Enable 1 Clock Enabled 0 Clock Disabled 16 VIP1_DP_EN R W 0h Video Input Port 1 Data Path...

Page 438: ...truments Incorporated High Definition Video Processing Subsystem HDVPSS Table 1 203 clkc_clken Register Field Descriptions continued Bit Field Type Reset Description 1 PRIM_DP_EN R W 0h Primary Video...

Page 439: ...29 Reserved R 0h Reserved 28 VIP2_CHR_DS_2_RST R W 0h Video Input Port 2 CHR_DS 2 Reset 1 Reset Enable 0 Reset Disable 27 VIP1_CHR_DS_2_RST R W 0h Video Input Port 1 CHR_DS 2 Reset 1 Reset Enable 0 R...

Page 440: ...Reset Disable 7 IND_TRANS1_DP_RST R W 0h Independent Transcode 1 to VIP1 Data Path Reset 1 Reset Enable 0 Reset Disable 6 COMP_DP_RST R W 0h Compositor Data Path Reset 1 Reset Enable 0 Reset Disable 5...

Page 441: ...escription 31 28 MAIN_DATAPATH_SELE CT R W 0h Main Datapath Register Field Enable 0000 All fields written 0001 Only vcomp_pip_select written 0010 Only vcomp_main_disable written 0011 Only hdcomp_dvo2_...

Page 442: ...011 Primary HQ Memory Input from VPDMA 100 Independent Transcode Input from Independent Transcode 101 Reserved 110 Reserved 111 Reserved 5 3 HDCOMP_DVO2_SELEC T R W 0h HDCOMP DVO2 Path Input Select 00...

Page 443: ...Type Reset Description 31 28 VIP1_DATAPATH_SELE CT R W 0h VIP1 Datapath Register Field Enable 0000 All fields written 0001 Only vip1_csc_src_select written 0010 Only vip1_sc_src_select written 0011 On...

Page 444: ...0h Video Input Port 1 Chroma Downsampler 2 Source Select 000 Path Disabled no input to CHR_DS 001 Source from Scaler SC_M 010 Source from Color Space Converter CSC 011 Source from VIP_PARSER A port 10...

Page 445: ...m HDVPSS Table 1 206 clkc_vip1dps Register Field Descriptions continued Bit Field Type Reset Description 2 0 VIP1_CSC_SRC_SELEC T R W 0h Video Input Port 1 CSC Source Select 000 Path Disabled 001 Sour...

Page 446: ...Type Reset Description 31 28 VIP2_DATAPATH_SELE CT R W 0h VIP2 Datapath Register Field Enable 0000 All fields written 0001 Only vip2_csc_src_select written 0010 Only vip2_sc_src_select written 0011 On...

Page 447: ...0h Video Input Port 2 Chroma Downsampler 2 Source Select 000 Path Disabled no input to CHR_DS 001 Source from Scaler SC_M 010 Source from Color Space Converter CSC 011 Source from VIP_PARSER A port 10...

Page 448: ...m HDVPSS Table 1 207 clkc_vip2dps Register Field Descriptions continued Bit Field Type Reset Description 2 0 VIP2_CSC_SRC_SELEC T R W 0h Video Input Port 2 CSC Source Select 000 Path Disabled 001 Sour...

Page 449: ...ld Descriptions Bit Field Type Reset Description 31 20 Reserved R 0h Reserved 19 DVO2_CLK_ON R W 0h Digital Video Output 2 output clock on 0 DVO2 output clock is off 0 1 DVO2 output clock is on 18 DVO...

Page 450: ...0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved SDVENC_ENABLE HD_VENC_D_ENABL E HD_VENC_A_ENABL E HD_VENC_D_ENABL E R 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only...

Page 451: ...bit n value after reset Table 1 210 clkc_range_map Register Field Descriptions Bit Field Type Reset Description 31 RANGE_REDUCTION_IN D2_ON R W 0h Range Reduction ON for IND2 transcode input 30 RANGE_...

Page 452: ...OMP _UNDERFLOW_STA T HDMI_UNDERFLOW _STAT R 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 211 clkc_underflow Register Field D...

Page 453: ...PDMA_int0_channel4_int_stat VPDMA Interrupt 0 Channel 4 Status Register Section 1 3 8 21 64h VPDMA_int0_channel4_int_mask VPDMA Interrupt 0 Channel 4 Mask Register Section 1 3 8 22 68h VPDMA_int0_chan...

Page 454: ...114h VPDMA_int2_channel6_int_mask VPDMA Interrupt 2 Channel 6 Mask Register Section 1 3 8 66 118h VPDMA_int2_client0_int_stat VPDMA Interrupt 2 Client 0 Status Register Section 1 3 8 67 11Ch VPDMA_in...

Page 455: ...1 3 8 110 38Ch VPDMA_vip1_lo_uv_cstat VPDMA VIP1 lo uv cstat Section 1 3 8 111 390h VPDMA_vip1_up_y_cstat VPDMA VIP1 up y cstat Section 1 3 8 112 394h VPDMA_vip1_up_uv_cstat VPDMA VIP1 up uv cstat Se...

Page 456: ...ly W1toCl Write 1 to clear bit n value after reset Table 1 213 VPDMA_pid Register Field Descriptions Bit Field Type Reset Description 31 30 SCHEME R 1h The scheme of the register used Currently this i...

Page 457: ...302 and described in Table 1 214 Figure 1 302 VPDMA_list_addr Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LIST_ADDR R W 0h LEGEND R W Read Write R R...

Page 458: ...available 23 21 Reserved R 0h 20 STOP W 0h This bit is written with the LIST_NUMBER field to stop a list When this bit is written a one the list specified by the LIST_NUMBER is sent a stop signal and...

Page 459: ...he LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0 20 LIST4_BUSY R 0h The list 4 is currently running Any attempt to load a new list to list 4 will resul...

Page 460: ...STS3 W 0h Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it 2 SYNC_LISTS2 W 0h Writing a 1 to this field causes a sync event to fire that c...

Page 461: ...et 10h reset 0h VPDMA_vpi_ctl_address is shown in Figure 1 305 and described in Table 1 217 Figure 1 305 VPDMA_vpi_ctl_address Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1...

Page 462: ...ffset 14h reset 0h VPDMA_vpi_ctl_data is shown in Figure 1 306 and described in Table 1 218 Figure 1 306 VPDMA_vpi_ctl_data Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...

Page 463: ...h 7 6 5 4 3 2 1 0 BLEND R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 219 VPDMA_bg_rgb Register Field Descriptions Bit Field Type Reset Description 3...

Page 464: ...1 20 19 18 17 16 Y R W 0h 15 14 13 12 11 10 9 8 CR R W 0h 7 6 5 4 3 2 1 0 CB R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 220 VPDMA_bg_yuv Register...

Page 465: ...offset 20h reset 0h VPDMA_descriptor_top is shown in Figure 1 309 and described in Table 1 221 Figure 1 309 VPDMA_descriptor_top Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Page 466: ...24h reset 0h VPDMA_descriptor_bottom is shown in Figure 1 310 and described in Table 1 222 Figure 1 310 VPDMA_descriptor_bottom Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11...

Page 467: ...28h reset 0h VPDMA_current_descriptor is shown in Figure 1 311 and described in Table 1 223 Figure 1 311 VPDMA_current_descriptor Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Page 468: ...et 0h VPDMA_descriptor_status_control is shown in Figure 1 312 and described in Table 1 224 Figure 1 312 VPDMA_descriptor_status_control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 469: ...ield to clear the value 30 INT_STAT_GRPX2 W 0h The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer This will fire before the destin...

Page 470: ...from the List Manager This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 11 6 Reserved R 0h 5 INT_STAT_HQ_VID3_CH ROMA W 0h Th...

Page 471: ...s it will have just been stored in the internal buffer The client dei_1_chroma will now accept a new descriptor from the List Manager This event will cause a one to be set in this register until clear...

Page 472: ...GRPX2 R W 0h The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 29 INT_MASK_GRPX1 R W 0h The inter...

Page 473: ...terrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 3 INT_MASK_HQ_VID2_CH ROMA R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int0 Write a 1...

Page 474: ...point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP1_MULT_ PORTB_SRC8 W 0h The last write DMA transaction...

Page 475: ...e external memory If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by...

Page 476: ...y the external memory If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point This event will cause a one to be set in this register until cleare...

Page 477: ...ll have just been stored in the internal buffer The client grpx1_clut_clt will now accept a new descriptor from the List Manager This event will cause a one to be set in this register until cleared by...

Page 478: ...vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 30 INT_MASK_VIP1_MULT_ PORTB_SRC8 R W 0h The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on...

Page 479: ...errupt event to trigger the interrupt signal 12 INT_MASK_VIP1_MULT_ PORTA_SRC6 R W 0h The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0 Write a 1 fo...

Page 480: ...0h The interrupt for Graphics 2 Stencil should generate an interrupt on interrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_GRPX2_STE NCIL R W 0h The int...

Page 481: ...ully empty at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP1_MULT_ ANCB_SRC8 W 0h The last writ...

Page 482: ...xternal memory If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by s...

Page 483: ...the external memory If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point This event will cause a one to be set in this register until cleare...

Page 484: ...he external memory If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point This event will cause a one to be set in this register until cleared...

Page 485: ...o trigger the interrupt signal 30 INT_MASK_VIP1_MULT_ ANCB_SRC8 R W 0h The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0 Write a 1 fo...

Page 486: ...1 for the interrupt event to trigger the interrupt signal 12 INT_MASK_VIP1_MULT_ ANCA_SRC6 R W 0h The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interr...

Page 487: ...ideo Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP1_MULT_ PORTB_SRC11 R W 0h The inter...

Page 488: ...y at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP2_MULT_ PORTB_SRC2 W 0h The last write DMA tr...

Page 489: ...by the external memory If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point This event will cause a one to be set in this register until clea...

Page 490: ...channel has been sent and received by the external memory If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point This event will cause a one to...

Page 491: ...he external memory If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point This event will cause a one to be set in this register until cleared...

Page 492: ...terrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 30 INT_MASK_VIP2_MULT_ PORTB_SRC2 R W 0h The interrupt for Video Input 2 Port B Channel 2 should generate an interr...

Page 493: ...n interrupt on interrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 12 INT_MASK_VIP2_MULT_ PORTA_SRC0 R W 0h The interrupt for Video Input 2 Port A Channel 0 should g...

Page 494: ...cillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP1_MULT_ ANCB_SRC11 R W 0h The interrupt for...

Page 495: ...fully empty at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP2_MULT_ ANCB_SRC2 W 0h The last wri...

Page 496: ...by the external memory If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point This event will cause a one to be set in this register until clea...

Page 497: ...ernal memory If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by sof...

Page 498: ...he external memory If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point This event will cause a one to be set in this register until cleared...

Page 499: ...trigger the interrupt signal 30 INT_MASK_VIP2_MULT_ ANCB_SRC2 R W 0h The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0 Write a 1 for...

Page 500: ...t on interrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 12 INT_MASK_VIP2_MULT_ ANCA_SRC0 R W 0h The interrupt for Video Input 2 Port A Ancillary Data Channel 0 shou...

Page 501: ...Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP2_MULT_ PORTB_SRC5 R W 0h The inter...

Page 502: ...nternal buffer The client trans2_chroma will now accept a new descriptor from the List Manager This event will cause a one to be set in this register until cleared by software Write a 1 to this field...

Page 503: ...e to be set in this register until cleared by software Write a 1 to this field to clear the value 21 INT_STAT_NF_LAST_LU MA W 0h The last read DMA transaction has occurred for channel nf_last_luma and...

Page 504: ...nel has not been setup for the client then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clea...

Page 505: ...Write a 1 to this field to clear the value 3 INT_STAT_VIP2_MULT_ ANCB_SRC7 W 0h The last write DMA transaction has completed for channel vip2_mult_ancb_src7 All data from the channel has been sent and...

Page 506: ...Type Reset Description 31 INT_MASK_TRANSCODE 2_CHROMA R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 30...

Page 507: ...a_int0 Write a 1 for the interrupt event to trigger the interrupt signal 11 INT_MASK_VIP2_MULT_ ANCB_SRC15 R W 0h The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an in...

Page 508: ...Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP2_MULT_ ANCB_SRC5 R W 0h The interrupt for...

Page 509: ...1 325 VPDMA_int0_channel6_int_stat Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved INT_STAT_OTHER R 0h...

Page 510: ...MA_int0_channel6_int_mask Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved INT_MASK_OTHER R 0h R W 0h L...

Page 511: ...ield to clear the value 30 INT_STAT_COMP_WRBK W 0h The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this clien...

Page 512: ...is client If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module This event will cause a one to be set in this register until cle...

Page 513: ...t If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module This event will cause a one to be set in this register until cleared by...

Page 514: ..._int0 Write a 1 for the interrupt event to trigger the interrupt signal 30 INT_MASK_COMP_WRB K R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int0 Write a 1 for the interrupt...

Page 515: ...rrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 3 INT_MASK_DEI_HQ_2_C HROMA R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int0 Write a 1 f...

Page 516: ...ed the End of Frame signal from the transmitting module This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 28 INT_STAT_VIP2_ANC...

Page 517: ...to this field to clear the value 20 INT_STAT_VPI_CTL W 0h The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this...

Page 518: ...eld to clear the value 10 INT_STAT_GRPX1_ST W 0h The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client I...

Page 519: ...nt If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module This event will cause a one to be set in this register until c...

Page 520: ...on 31 30 Reserved R 0h 29 INT_MASK_VIP2_ANC_B R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 28 INT_MAS...

Page 521: ...ate an interrupt on interrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 10 INT_MASK_GRPX1_ST R W 0h The interrupt for should generate an interrupt on interrupt vpdma...

Page 522: ...orporated High Definition Video Processing Subsystem HDVPSS Table 1 242 VPDMA_int0_client1_int_mask Register Field Descriptions continued Bit Field Type Reset Description 0 INT_MASK_GRPX2_DAT A R W 0h...

Page 523: ...been received by the list manager with a source value of 15 This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_CONT...

Page 524: ...d Interrupt Control Descriptor has been received by the list manager with a source value of 1 This event will cause a one to be set in this register until cleared by software Write a 1 to this field t...

Page 525: ...scriptor for that channel This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 4 INT_STAT_LIST2_COMP LETE W 0h List 2 has complet...

Page 526: ...r reset Table 1 244 VPDMA_int0_list0_int_mask Register Field Descriptions Bit Field Type Reset Description 31 INT_MASK_CONTROL_D ESCRIPTOR_INT15 R W 0h The interrupt for should generate an interrupt o...

Page 527: ...ld generate an interrupt on interrupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 13 INT_MASK_LIST6_NOTIF Y R W 0h The interrupt for should generate an interrupt on in...

Page 528: ...rupt vpdma_int0 Write a 1 for the interrupt event to trigger the interrupt signal 2 INT_MASK_LIST1_COMP LETE R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int0 Write a 1 for...

Page 529: ...ield to clear the value 30 INT_STAT_GRPX2 W 0h The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer This will fire before the destin...

Page 530: ...from the List Manager This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 11 6 Reserved R 0h 5 INT_STAT_HQ_VID3_CH ROMA W 0h Th...

Page 531: ...s it will have just been stored in the internal buffer The client dei_1_chroma will now accept a new descriptor from the List Manager This event will cause a one to be set in this register until clear...

Page 532: ...GRPX2 R W 0h The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 29 INT_MASK_GRPX1 R W 0h The inter...

Page 533: ...terrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 3 INT_MASK_HQ_VID2_CH ROMA R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int1 Write a 1...

Page 534: ...point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP1_MULT_ PORTB_SRC8 W 0h The last write DMA transaction...

Page 535: ...e external memory If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by...

Page 536: ...y the external memory If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point This event will cause a one to be set in this register until cleare...

Page 537: ...ll have just been stored in the internal buffer The client grpx1_clut_clt will now accept a new descriptor from the List Manager This event will cause a one to be set in this register until cleared by...

Page 538: ...vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 30 INT_MASK_VIP1_MULT_ PORTB_SRC8 R W 0h The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on...

Page 539: ...errupt event to trigger the interrupt signal 12 INT_MASK_VIP1_MULT_ PORTA_SRC6 R W 0h The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1 Write a 1 fo...

Page 540: ...0h The interrupt for Graphics 2 Stencil should generate an interrupt on interrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_GRPX2_STE NCIL R W 0h The int...

Page 541: ...ully empty at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP1_MULT_ ANCB_SRC8 W 0h The last writ...

Page 542: ...xternal memory If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by s...

Page 543: ...the external memory If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point This event will cause a one to be set in this register until cleare...

Page 544: ...he external memory If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point This event will cause a one to be set in this register until cleared...

Page 545: ...o trigger the interrupt signal 30 INT_MASK_VIP1_MULT_ ANCB_SRC8 R W 0h The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1 Write a 1 fo...

Page 546: ...1 for the interrupt event to trigger the interrupt signal 12 INT_MASK_VIP1_MULT_ ANCA_SRC6 R W 0h The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interr...

Page 547: ...ideo Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP1_MULT_ PORTB_SRC11 R W 0h The inter...

Page 548: ...y at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP2_MULT_ PORTB_SRC2 W 0h The last write DMA tr...

Page 549: ...by the external memory If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point This event will cause a one to be set in this register until clea...

Page 550: ...channel has been sent and received by the external memory If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point This event will cause a one to...

Page 551: ...he external memory If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point This event will cause a one to be set in this register until cleared...

Page 552: ...terrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 30 INT_MASK_VIP2_MULT_ PORTB_SRC2 R W 0h The interrupt for Video Input 2 Port B Channel 2 should generate an interr...

Page 553: ...n interrupt on interrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 12 INT_MASK_VIP2_MULT_ PORTA_SRC0 R W 0h The interrupt for Video Input 2 Port A Channel 0 should g...

Page 554: ...cillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP1_MULT_ ANCB_SRC11 R W 0h The interrupt for...

Page 555: ...fully empty at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP2_MULT_ ANCB_SRC2 W 0h The last wri...

Page 556: ...by the external memory If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point This event will cause a one to be set in this register until clea...

Page 557: ...ernal memory If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by sof...

Page 558: ...he external memory If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point This event will cause a one to be set in this register until cleared...

Page 559: ...trigger the interrupt signal 30 INT_MASK_VIP2_MULT_ ANCB_SRC2 R W 0h The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1 Write a 1 for...

Page 560: ...t on interrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 12 INT_MASK_VIP2_MULT_ ANCA_SRC0 R W 0h The interrupt for Video Input 2 Port A Ancillary Data Channel 0 shou...

Page 561: ...Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP2_MULT_ PORTB_SRC5 R W 0h The inter...

Page 562: ...nternal buffer The client trans2_chroma will now accept a new descriptor from the List Manager This event will cause a one to be set in this register until cleared by software Write a 1 to this field...

Page 563: ...e to be set in this register until cleared by software Write a 1 to this field to clear the value 21 INT_STAT_NF_LAST_LU MA W 0h The last read DMA transaction has occurred for channel nf_last_luma and...

Page 564: ...nel has not been setup for the client then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clea...

Page 565: ...Write a 1 to this field to clear the value 3 INT_STAT_VIP2_MULT_ ANCB_SRC7 W 0h The last write DMA transaction has completed for channel vip2_mult_ancb_src7 All data from the channel has been sent and...

Page 566: ...Type Reset Description 31 INT_MASK_TRANSCODE 2_CHROMA R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 30...

Page 567: ...a_int1 Write a 1 for the interrupt event to trigger the interrupt signal 11 INT_MASK_VIP2_MULT_ ANCB_SRC15 R W 0h The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an in...

Page 568: ...Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP2_MULT_ ANCB_SRC5 R W 0h The interrupt for...

Page 569: ...1 345 VPDMA_int1_channel6_int_stat Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved INT_STAT_OTHER R 0h...

Page 570: ...MA_int1_channel6_int_mask Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved INT_MASK_OTHER R 0h R W 0h L...

Page 571: ...ield to clear the value 30 INT_STAT_COMP_WRBK W 0h The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this clien...

Page 572: ...is client If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module This event will cause a one to be set in this register until cle...

Page 573: ...t If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module This event will cause a one to be set in this register until cleared by...

Page 574: ..._int1 Write a 1 for the interrupt event to trigger the interrupt signal 30 INT_MASK_COMP_WRB K R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int1 Write a 1 for the interrupt...

Page 575: ...rrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 3 INT_MASK_DEI_HQ_2_C HROMA R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int1 Write a 1 f...

Page 576: ...ed the End of Frame signal from the transmitting module This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 28 INT_STAT_VIP2_ANC...

Page 577: ...to this field to clear the value 20 INT_STAT_VPI_CTL W 0h The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this...

Page 578: ...eld to clear the value 10 INT_STAT_GRPX1_ST W 0h The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client I...

Page 579: ...nt If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module This event will cause a one to be set in this register until c...

Page 580: ...on 31 30 Reserved R 0h 29 INT_MASK_VIP2_ANC_B R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 28 INT_MAS...

Page 581: ...ate an interrupt on interrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 10 INT_MASK_GRPX1_ST R W 0h The interrupt for should generate an interrupt on interrupt vpdma...

Page 582: ...orporated High Definition Video Processing Subsystem HDVPSS Table 1 262 VPDMA_int1_client1_int_mask Register Field Descriptions continued Bit Field Type Reset Description 0 INT_MASK_GRPX2_DAT A R W 0h...

Page 583: ...been received by the list manager with a source value of 15 This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_CONT...

Page 584: ...d Interrupt Control Descriptor has been received by the list manager with a source value of 1 This event will cause a one to be set in this register until cleared by software Write a 1 to this field t...

Page 585: ...scriptor for that channel This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 4 INT_STAT_LIST2_COMP LETE W 0h List 2 has complet...

Page 586: ...r reset Table 1 264 VPDMA_int1_list0_int_mask Register Field Descriptions Bit Field Type Reset Description 31 INT_MASK_CONTROL_D ESCRIPTOR_INT15 R W 0h The interrupt for should generate an interrupt o...

Page 587: ...ld generate an interrupt on interrupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 13 INT_MASK_LIST6_NOTIF Y R W 0h The interrupt for should generate an interrupt on in...

Page 588: ...rupt vpdma_int1 Write a 1 for the interrupt event to trigger the interrupt signal 2 INT_MASK_LIST1_COMP LETE R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int1 Write a 1 for...

Page 589: ...ield to clear the value 30 INT_STAT_GRPX2 W 0h The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer This will fire before the destin...

Page 590: ...from the List Manager This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 11 6 Reserved R 0h 5 INT_STAT_HQ_VID3_CH ROMA W 0h Th...

Page 591: ...s it will have just been stored in the internal buffer The client dei_1_chroma will now accept a new descriptor from the List Manager This event will cause a one to be set in this register until clear...

Page 592: ...GRPX2 R W 0h The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 29 INT_MASK_GRPX1 R W 0h The inter...

Page 593: ...terrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 3 INT_MASK_HQ_VID2_CH ROMA R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int2 Write a 1...

Page 594: ...point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP1_MULT_ PORTB_SRC8 W 0h The last write DMA transaction...

Page 595: ...e external memory If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by...

Page 596: ...y the external memory If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point This event will cause a one to be set in this register until cleare...

Page 597: ...ll have just been stored in the internal buffer The client grpx1_clut_clt will now accept a new descriptor from the List Manager This event will cause a one to be set in this register until cleared by...

Page 598: ...vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 30 INT_MASK_VIP1_MULT_ PORTB_SRC8 R W 0h The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on...

Page 599: ...errupt event to trigger the interrupt signal 12 INT_MASK_VIP1_MULT_ PORTA_SRC6 R W 0h The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int2 Write a 1 fo...

Page 600: ...0h The interrupt for Graphics 2 Stencil should generate an interrupt on interrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_GRPX2_STE NCIL R W 0h The int...

Page 601: ...ully empty at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP1_MULT_ ANCB_SRC8 W 0h The last writ...

Page 602: ...xternal memory If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by s...

Page 603: ...the external memory If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point This event will cause a one to be set in this register until cleare...

Page 604: ...he external memory If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point This event will cause a one to be set in this register until cleared...

Page 605: ...o trigger the interrupt signal 30 INT_MASK_VIP1_MULT_ ANCB_SRC8 R W 0h The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int2 Write a 1 fo...

Page 606: ...1 for the interrupt event to trigger the interrupt signal 12 INT_MASK_VIP1_MULT_ ANCA_SRC6 R W 0h The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interr...

Page 607: ...ideo Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP1_MULT_ PORTB_SRC11 R W 0h The inter...

Page 608: ...y at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP2_MULT_ PORTB_SRC2 W 0h The last write DMA tr...

Page 609: ...by the external memory If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point This event will cause a one to be set in this register until clea...

Page 610: ...channel has been sent and received by the external memory If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point This event will cause a one to...

Page 611: ...he external memory If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point This event will cause a one to be set in this register until cleared...

Page 612: ...terrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 30 INT_MASK_VIP2_MULT_ PORTB_SRC2 R W 0h The interrupt for Video Input 2 Port B Channel 2 should generate an interr...

Page 613: ...n interrupt on interrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 12 INT_MASK_VIP2_MULT_ PORTA_SRC0 R W 0h The interrupt for Video Input 2 Port A Channel 0 should g...

Page 614: ...cillary Data Channel 12 should generate an interrupt on interrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP1_MULT_ ANCB_SRC11 R W 0h The interrupt for...

Page 615: ...fully empty at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP2_MULT_ ANCB_SRC2 W 0h The last wr...

Page 616: ...by the external memory If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point This event will cause a one to be set in this register until clea...

Page 617: ...ernal memory If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by sof...

Page 618: ...he external memory If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point This event will cause a one to be set in this register until cleared...

Page 619: ...trigger the interrupt signal 30 INT_MASK_VIP2_MULT_ ANCB_SRC2 R W 0h The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int2 Write a 1 for...

Page 620: ...t on interrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 12 INT_MASK_VIP2_MULT_ ANCA_SRC0 R W 0h The interrupt for Video Input 2 Port A Ancillary Data Channel 0 shou...

Page 621: ...Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP2_MULT_ PORTB_SRC5 R W 0h The inter...

Page 622: ...nternal buffer The client trans2_chroma will now accept a new descriptor from the List Manager This event will cause a one to be set in this register until cleared by software Write a 1 to this field...

Page 623: ...e to be set in this register until cleared by software Write a 1 to this field to clear the value 21 INT_STAT_NF_LAST_LU MA W 0h The last read DMA transaction has occurred for channel nf_last_luma and...

Page 624: ...nel has not been setup for the client then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clea...

Page 625: ...Write a 1 to this field to clear the value 3 INT_STAT_VIP2_MULT_ ANCB_SRC7 W 0h The last write DMA transaction has completed for channel vip2_mult_ancb_src7 All data from the channel has been sent and...

Page 626: ...Type Reset Description 31 INT_MASK_TRANSCODE 2_CHROMA R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 3...

Page 627: ...a_int2 Write a 1 for the interrupt event to trigger the interrupt signal 11 INT_MASK_VIP2_MULT_ ANCB_SRC15 R W 0h The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an in...

Page 628: ...Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP2_MULT_ ANCB_SRC5 R W 0h The interrupt for...

Page 629: ...1 365 VPDMA_int2_channel6_int_stat Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved INT_STAT_OTHER R 0h...

Page 630: ...DMA_int2_channel6_int_mask Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved INT_MASK_OTHER R 0h R W 0h...

Page 631: ...field to clear the value 30 INT_STAT_COMP_WRBK W 0h The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this clie...

Page 632: ...is client If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module This event will cause a one to be set in this register until cle...

Page 633: ...t If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module This event will cause a one to be set in this register until cleared by...

Page 634: ..._int2 Write a 1 for the interrupt event to trigger the interrupt signal 30 INT_MASK_COMP_WRB K R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int2 Write a 1 for the interrupt...

Page 635: ...rrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 3 INT_MASK_DEI_HQ_2_C HROMA R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int2 Write a 1 f...

Page 636: ...ed the End of Frame signal from the transmitting module This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 28 INT_STAT_VIP2_ANC...

Page 637: ...to this field to clear the value 20 INT_STAT_VPI_CTL W 0h The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this...

Page 638: ...eld to clear the value 10 INT_STAT_GRPX1_ST W 0h The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client I...

Page 639: ...nt If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module This event will cause a one to be set in this register until c...

Page 640: ...on 31 30 Reserved R 0h 29 INT_MASK_VIP2_ANC_B R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 28 INT_MAS...

Page 641: ...ate an interrupt on interrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 10 INT_MASK_GRPX1_ST R W 0h The interrupt for should generate an interrupt on interrupt vpdma...

Page 642: ...orporated High Definition Video Processing Subsystem HDVPSS Table 1 282 VPDMA_int2_client1_int_mask Register Field Descriptions continued Bit Field Type Reset Description 0 INT_MASK_GRPX2_DAT A R W 0h...

Page 643: ...been received by the list manager with a source value of 15 This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_CON...

Page 644: ...d Interrupt Control Descriptor has been received by the list manager with a source value of 1 This event will cause a one to be set in this register until cleared by software Write a 1 to this field t...

Page 645: ...scriptor for that channel This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 4 INT_STAT_LIST2_COMP LETE W 0h List 2 has complet...

Page 646: ...er reset Table 1 284 VPDMA_int2_list0_int_mask Register Field Descriptions Bit Field Type Reset Description 31 INT_MASK_CONTROL_D ESCRIPTOR_INT15 R W 0h The interrupt for should generate an interrupt...

Page 647: ...ld generate an interrupt on interrupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 13 INT_MASK_LIST6_NOTIF Y R W 0h The interrupt for should generate an interrupt on in...

Page 648: ...rupt vpdma_int2 Write a 1 for the interrupt event to trigger the interrupt signal 2 INT_MASK_LIST1_COMP LETE R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int2 Write a 1 for...

Page 649: ...field to clear the value 30 INT_STAT_GRPX2 W 0h The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer This will fire before the desti...

Page 650: ...from the List Manager This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 11 6 Reserved R 0h 5 INT_STAT_HQ_VID3_CH ROMA W 0h Th...

Page 651: ...s it will have just been stored in the internal buffer The client dei_1_chroma will now accept a new descriptor from the List Manager This event will cause a one to be set in this register until clear...

Page 652: ..._GRPX2 R W 0h The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 29 INT_MASK_GRPX1 R W 0h The inte...

Page 653: ...terrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 3 INT_MASK_HQ_VID2_CH ROMA R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int3 Write a 1...

Page 654: ...point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP1_MULT_ PORTB_SRC8 W 0h The last write DMA transaction...

Page 655: ...e external memory If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by...

Page 656: ...y the external memory If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point This event will cause a one to be set in this register until cleare...

Page 657: ...ll have just been stored in the internal buffer The client grpx1_clut_clt will now accept a new descriptor from the List Manager This event will cause a one to be set in this register until cleared by...

Page 658: ...t vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 30 INT_MASK_VIP1_MULT_ PORTB_SRC8 R W 0h The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on...

Page 659: ...errupt event to trigger the interrupt signal 12 INT_MASK_VIP1_MULT_ PORTA_SRC6 R W 0h The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int3 Write a 1 fo...

Page 660: ...0h The interrupt for Graphics 2 Stencil should generate an interrupt on interrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_GRPX2_STE NCIL R W 0h The int...

Page 661: ...fully empty at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP1_MULT_ ANCB_SRC8 W 0h The last wri...

Page 662: ...xternal memory If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by s...

Page 663: ...the external memory If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point This event will cause a one to be set in this register until cleare...

Page 664: ...he external memory If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point This event will cause a one to be set in this register until cleared...

Page 665: ...o trigger the interrupt signal 30 INT_MASK_VIP1_MULT_ ANCB_SRC8 R W 0h The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int3 Write a 1 fo...

Page 666: ...1 for the interrupt event to trigger the interrupt signal 12 INT_MASK_VIP1_MULT_ ANCA_SRC6 R W 0h The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interr...

Page 667: ...ideo Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP1_MULT_ PORTB_SRC11 R W 0h The inter...

Page 668: ...ty at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP2_MULT_ PORTB_SRC2 W 0h The last write DMA t...

Page 669: ...by the external memory If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point This event will cause a one to be set in this register until clea...

Page 670: ...channel has been sent and received by the external memory If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point This event will cause a one to...

Page 671: ...he external memory If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point This event will cause a one to be set in this register until cleared...

Page 672: ...terrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 30 INT_MASK_VIP2_MULT_ PORTB_SRC2 R W 0h The interrupt for Video Input 2 Port B Channel 2 should generate an interr...

Page 673: ...n interrupt on interrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 12 INT_MASK_VIP2_MULT_ PORTA_SRC0 R W 0h The interrupt for Video Input 2 Port A Channel 0 should g...

Page 674: ...cillary Data Channel 12 should generate an interrupt on interrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP1_MULT_ ANCB_SRC11 R W 0h The interrupt for...

Page 675: ...fully empty at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_VIP2_MULT_ ANCB_SRC2 W 0h The last wr...

Page 676: ...by the external memory If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point This event will cause a one to be set in this register until clea...

Page 677: ...ernal memory If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by sof...

Page 678: ...he external memory If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point This event will cause a one to be set in this register until cleared...

Page 679: ...trigger the interrupt signal 30 INT_MASK_VIP2_MULT_ ANCB_SRC2 R W 0h The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int3 Write a 1 for...

Page 680: ...t on interrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 12 INT_MASK_VIP2_MULT_ ANCA_SRC0 R W 0h The interrupt for Video Input 2 Port A Ancillary Data Channel 0 shou...

Page 681: ...Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP2_MULT_ PORTB_SRC5 R W 0h The inter...

Page 682: ...nternal buffer The client trans2_chroma will now accept a new descriptor from the List Manager This event will cause a one to be set in this register until cleared by software Write a 1 to this field...

Page 683: ...e to be set in this register until cleared by software Write a 1 to this field to clear the value 21 INT_STAT_NF_LAST_LU MA W 0h The last read DMA transaction has occurred for channel nf_last_luma and...

Page 684: ...nel has not been setup for the client then the client will be fully empty at this point This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clea...

Page 685: ...Write a 1 to this field to clear the value 3 INT_STAT_VIP2_MULT_ ANCB_SRC7 W 0h The last write DMA transaction has completed for channel vip2_mult_ancb_src7 All data from the channel has been sent and...

Page 686: ...Type Reset Description 31 INT_MASK_TRANSCODE 2_CHROMA R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 3...

Page 687: ...a_int3 Write a 1 for the interrupt event to trigger the interrupt signal 11 INT_MASK_VIP2_MULT_ ANCB_SRC15 R W 0h The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an in...

Page 688: ...Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 1 INT_MASK_VIP2_MULT_ ANCB_SRC5 R W 0h The interrupt for...

Page 689: ...1 385 VPDMA_int3_channel6_int_stat Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved INT_STAT_OTHER R 0h...

Page 690: ...DMA_int3_channel6_int_mask Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved INT_MASK_OTHER R 0h R W 0h...

Page 691: ...field to clear the value 30 INT_STAT_COMP_WRBK W 0h The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this clie...

Page 692: ...is client If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module This event will cause a one to be set in this register until cle...

Page 693: ...t If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module This event will cause a one to be set in this register until cleared by...

Page 694: ..._int3 Write a 1 for the interrupt event to trigger the interrupt signal 30 INT_MASK_COMP_WRB K R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int3 Write a 1 for the interrupt...

Page 695: ...rrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 3 INT_MASK_DEI_HQ_2_C HROMA R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int3 Write a 1 f...

Page 696: ...ed the End of Frame signal from the transmitting module This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 28 INT_STAT_VIP2_ANC...

Page 697: ...to this field to clear the value 20 INT_STAT_VPI_CTL W 0h The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this...

Page 698: ...eld to clear the value 10 INT_STAT_GRPX1_ST W 0h The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client I...

Page 699: ...nt If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module This event will cause a one to be set in this register until c...

Page 700: ...on 31 30 Reserved R 0h 29 INT_MASK_VIP2_ANC_B R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 28 INT_MAS...

Page 701: ...ate an interrupt on interrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 10 INT_MASK_GRPX1_ST R W 0h The interrupt for should generate an interrupt on interrupt vpdma...

Page 702: ...orporated High Definition Video Processing Subsystem HDVPSS Table 1 302 VPDMA_int3_client1_int_mask Register Field Descriptions continued Bit Field Type Reset Description 0 INT_MASK_GRPX2_DAT A R W 0h...

Page 703: ...been received by the list manager with a source value of 15 This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 30 INT_STAT_CON...

Page 704: ...d Interrupt Control Descriptor has been received by the list manager with a source value of 1 This event will cause a one to be set in this register until cleared by software Write a 1 to this field t...

Page 705: ...scriptor for that channel This event will cause a one to be set in this register until cleared by software Write a 1 to this field to clear the value 4 INT_STAT_LIST2_COMP LETE W 0h List 2 has complet...

Page 706: ...er reset Table 1 304 VPDMA_int3_list0_int_mask Register Field Descriptions Bit Field Type Reset Description 31 INT_MASK_CONTROL_D ESCRIPTOR_INT15 R W 0h The interrupt for should generate an interrupt...

Page 707: ...ld generate an interrupt on interrupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 13 INT_MASK_LIST6_NOTIF Y R W 0h The interrupt for should generate an interrupt on in...

Page 708: ...rupt vpdma_int3 Write a 1 for the interrupt event to trigger the interrupt signal 2 INT_MASK_LIST1_COMP LETE R W 0h The interrupt for should generate an interrupt on interrupt vpdma_int3 Write a 1 for...

Page 709: ...y 32 to get the actual number of cycles This value is only accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins 15 BUSY R 0h Signals if the...

Page 710: ...ly accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h Th...

Page 711: ...ly accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h Th...

Page 712: ...y 32 to get the actual number of cycles This value is only accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins 15 BUSY R 0h Signals if the...

Page 713: ...ly accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h Th...

Page 714: ...y 32 to get the actual number of cycles This value is only accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins 15 BUSY R 0h Signals if the...

Page 715: ...accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The...

Page 716: ...ly accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h Th...

Page 717: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 718: ...e for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The number o...

Page 719: ...o get the actual number of cycles This value is only accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins 15 BUSY R 0h Signals if the clien...

Page 720: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 721: ...r the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The number of cl...

Page 722: ...ate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The number...

Page 723: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 724: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 725: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 726: ...ate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The number...

Page 727: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 728: ...ate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The number...

Page 729: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 730: ...ate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The number...

Page 731: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 732: ...ate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The number...

Page 733: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 734: ...e for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The number o...

Page 735: ...e for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The number o...

Page 736: ...e for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The number o...

Page 737: ...ate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The number...

Page 738: ...ccurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The nu...

Page 739: ...accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The...

Page 740: ...accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The...

Page 741: ...ly accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h Th...

Page 742: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 743: ...for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The number of...

Page 744: ...ly accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h Th...

Page 745: ...to get the actual number of cycles This value is only accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins 15 BUSY R 0h Signals if the cli...

Page 746: ...ccurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The nu...

Page 747: ...to get the actual number of cycles This value is only accurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins 15 BUSY R 0h Signals if the cli...

Page 748: ...ccurate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The nu...

Page 749: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 750: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 751: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 752: ...urate for the current frame The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible 23 16 REQ_RATE R 0h The numb...

Page 753: ...Ch HD_VENC_D_cfg7 Reserved Register Section 1 3 9 8 20h HD_VENC_D_cfg8 Reserved Register Section 1 3 9 9 24h HD_VENC_D_cfg9 Reserved Register Section 1 3 9 10 28h HD_VENC_D_cfg10 Frame Size Register S...

Page 754: ...T R W 0h This bit will start the operation of encoder 0 encoder is in standby mode no data and signals will be outputted 1 encoder is in the normal operation mode During the normal operation this bit...

Page 755: ...e equals to the pixel rate 011 Three channel 10 bit video streams with dedicated HS VS FID ACTVID sync signals The three channel component digital video can be RGB or YCbCr444 format It can be used fo...

Page 756: ...Field Descriptions Bit Field Type Reset Description 31 29 Reserved R 0h Reserved 28 16 B0 R W 0h Coefficients of color space converter This coefficient is a real number in the range of 4 to 4 represen...

Page 757: ...10 9 8 Reserved C0 R 0h R W 0h 7 6 5 4 3 2 1 0 C0 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 352 HD_VENC_D_cfg2 Register Field Descriptions Bit F...

Page 758: ...10 9 8 Reserved B1 R 0h R W 0h 7 6 5 4 3 2 1 0 B1 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 353 HD_VENC_D_cfg3 Register Field Descriptions Bit F...

Page 759: ...1 10 9 8 Reserved A2 R 0h R W 0h 7 6 5 4 3 2 1 0 A2 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 354 HD_VENC_D_cfg4 Register Field Descriptions Bit...

Page 760: ...ead only W1toCl Write 1 to clear bit n value after reset Table 1 355 HD_VENC_D_cfg5 Register Field Descriptions Bit Field Type Reset Description 31 28 Reserved R 0h Reserved 27 16 D0 R W 0h Coefficien...

Page 761: ...W 0h R W 0h 7 6 5 4 3 2 1 0 D1 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 356 HD_VENC_D_cfg6 Register Field Descriptions Bit Field Type Reset Des...

Page 762: ...egister offset 1Ch reset 0h HD_VENC_D_cfg7 is shown in Figure 1 444 and described in Table 1 357 Reserved Register Figure 1 444 HD_VENC_D_cfg7 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 763: ...egister offset 20h reset 0h HD_VENC_D_cfg8 is shown in Figure 1 445 and described in Table 1 358 Reserved Register Figure 1 445 HD_VENC_D_cfg8 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 764: ...egister offset 24h reset 0h HD_VENC_D_cfg9 is shown in Figure 1 446 and described in Table 1 359 Reserved Register Figure 1 446 HD_VENC_D_cfg9 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 765: ...ze Register Figure 1 447 HD_VENC_D_cfg10 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 LINES R W 0h 15 14 13 12 11 10 9 8 LINES PIXELS R W 0h R W 0h 7 6 5 4 3 2 1 0 PIXELS R W...

Page 766: ...gister offset 2Ch reset 0h HD_VENC_D_cfg11 is shown in Figure 1 448 and described in Table 1 361 Reserved Register Figure 1 448 HD_VENC_D_cfg11 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 767: ...e Pixels per Line Register Figure 1 449 HD_VENC_D_cfg12 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 ACT_PIX R W 0h 15 14 13 12 11 10 9 8 ACT_PIX Reserved R W 0h R 0h 7 6 5 4...

Page 768: ...egister Figure 1 450 HD_VENC_D_cfg13 Register 31 30 29 28 27 26 25 24 DELAY_VENC Reserved R W 0h R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved...

Page 769: ...gister offset 38h reset 0h HD_VENC_D_cfg14 is shown in Figure 1 451 and described in Table 1 364 Reserved Register Figure 1 451 HD_VENC_D_cfg14 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 770: ...0h 15 14 13 12 11 10 9 8 DVO_AVD_HW DVO_AVST_H R W 0h R W 0h 7 6 5 4 3 2 1 0 DVO_AVST_H R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 365 HD_VENC_D_c...

Page 771: ...Reserved R 0h 23 22 21 20 19 18 17 16 DVO_AVST_V1 R W 0h 15 14 13 12 11 10 9 8 DVO_AVST_V1 DVO_HS_ST R W 0h R W 0h 7 6 5 4 3 2 1 0 DVO_HS_ST R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to...

Page 772: ...19 18 17 16 DVO_AVD_VW1 R W 0h 15 14 13 12 11 10 9 8 DVO_AVD_VW1 DVO_AVST_V2 R W 0h R W 0h 7 6 5 4 3 2 1 0 DVO_AVST_V2 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value aft...

Page 773: ...VW2 R W 0h R W 0h 7 6 5 4 3 2 1 0 DVO_AVD_VW2 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 368 HD_VENC_D_cfg18 Register Field Descriptions Bit Field...

Page 774: ...ST1 R W 0h 15 14 13 12 11 10 9 8 DVO_FID_ST1 DVO_VS_ST2 R W 0h R W 0h 7 6 5 4 3 2 1 0 DVO_VS_ST2 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 369 HD...

Page 775: ...6 5 4 3 2 1 0 DVO_FID_ST2 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 370 HD_VENC_D_cfg20 Register Field Descriptions Bit Field Type Reset Descript...

Page 776: ...Reserved R 0h 23 22 21 20 19 18 17 16 OSD_AVD_HW R W 0h 15 14 13 12 11 10 9 8 OSD_AVD_HW OSD_AVST_H R W 0h R W 0h 7 6 5 4 3 2 1 0 OSD_AVST_H R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to...

Page 777: ...31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 OSD_AVST_V1 R W 0h 15 14 13 12 11 10 9 8 OSD_AVST_V1 Reserved R W 0h R 0h 7 6 5 4 3 2 1 0 Reserved R 0h LEGEND R W Read Write R Read only...

Page 778: ...0h 23 22 21 20 19 18 17 16 OSD_AVD_VW1 R W 0h 15 14 13 12 11 10 9 8 OSD_AVD_VW1 OSD_AVST_V2 R W 0h R W 0h 7 6 5 4 3 2 1 0 OSD_AVST_V2 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear...

Page 779: ...ol Register Figure 1 461 HD_VENC_D_cfg24 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved OSD_AVD_VW2 R 0h R W 0h 7 6 5 4 3 2 1 0 OSD...

Page 780: ...t n value after reset Table 1 375 HD_VENC_D_cfg25 Register Field Descriptions Bit Field Type Reset Description 31 24 Reserved R 0h Reserved 23 12 OSD_FID_ST1 R W 0h This parameter defines the frame li...

Page 781: ...t0 a R W 0h R W 0h 7 6 5 4 3 2 1 0 lut0 a R W 0h LEGEND R W Read Write R Read only n value after reset Table 1 376 HD_VEND_D_GAMMA_LUT Register Field Descriptions Bit Field Type Reset Description 31 3...

Page 782: ...modified Table 1 377 NOISE_FILTER REGISTERS Offset Acronym Register Name Section 0h nf_reg0 NF Mode Reg Section 1 3 10 1 4h nf_reg1 NF Video Size Config Reg Section 1 3 10 2 8h nf_reg2 NF Spatial Str...

Page 783: ...sters get updated at the end of current frame processing When set to 0 updates are not done allowing next frame to use the same initial frame noise value used by the previous frame 11 NF_LOAD_FRAME_NO...

Page 784: ...1 379 Figure 1 465 nf_reg1 Register 31 30 29 28 27 26 25 24 Reserved HEIGHT R 0h R W 0h 23 22 21 20 19 18 17 16 HEIGHT R W 0h 15 14 13 12 11 10 9 8 Reserved WIDTH R 0h R W 0h 7 6 5 4 3 2 1 0 WIDTH R...

Page 785: ...7 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 SPATIAL_STRENGTH_Y_HIGH R W 8h 7 6 5 4 3 2 1 0 SPATIAL_STRENGTH_Y_LOW R W 8h LEGEND R W Read Write R Read only W1to...

Page 786: ...9 8 SPATIAL_STRENGTH_U_HIGH R W 10h 7 6 5 4 3 2 1 0 SPATIAL_STRENGTH_U_LOW R W 10h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 381 nf_reg3 Register Field...

Page 787: ...25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved TEMPORAL_FILTER_TRIGGER_NOISE R 0h R W 6h 7 6 5 4 3 2 1 0 Reserved TEMPORAL_STRENGTH R 0h R W Dh LEGEND R W Re...

Page 788: ...1 469 nf_reg5 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved MAX_NOISE R 0h R W Ah 7 6 5 4 3 2 1 0 MAX_NOISE NOISE_IIR_COEFFICIENT...

Page 789: ...1 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved PURE_WHITE_THRESHOLD R 0h R W Fh 7 6 5 4 3 2 1 0 Reserved PURE_BLACK_THRESHOLD R 0h R W Fh LEGEND R W Read Write R Read only W1toCl Write...

Page 790: ...71 nf_reg7 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved FRAME_NOISE_READ_INDEX R 0h R W 0h LEGEND R...

Page 791: ...eserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved FRAME_NOISE_Y R 0h R W 0h 7 6 5 4 3 2 1 0 FRAME_NOISE_Y R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to cle...

Page 792: ...2 1 0 FRAME_NOISE_V R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 387 nf_reg9 Register Field Descriptions Bit Field Type Reset Description 31 29 Rese...

Page 793: ...fg_sc6 SC Vertical Scaler Config Reg 3 Section 1 3 11 7 20h SC_M_cfg_sc8 SC Horizontal Scaler Config Reg 0 Section 1 3 11 8 24h SC_M_cfg_sc9 SC Horizontal Scaler Config Reg 1 Section 1 3 11 9 28h SC_M...

Page 794: ...performing interlacing 15 CFG_TRIM R W 0h Trimming enable When 1 the input image whose size is specified by orgW and orgH registers is trimmed to the size with srcW and srcH from the offset specified...

Page 795: ...s 0 5 SR 0 25 dcm_2x and horizontal polyphase filter both are enabled SR 0 25 dcm_4x is enabled horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass 0 25 SR 0 125 dcm_4x and horiz...

Page 796: ...CFG_ROW_ACC_INC R W 0h 15 14 13 12 11 10 9 8 CFG_ROW_ACC_INC R W 0h 7 6 5 4 3 2 1 0 CFG_ROW_ACC_INC R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 39...

Page 797: ...FSET R 0h R W 0h 23 22 21 20 19 18 17 16 CFG_ROW_ACC_OFFSET R W 0h 15 14 13 12 11 10 9 8 CFG_ROW_ACC_OFFSET R W 0h 7 6 5 4 3 2 1 0 CFG_ROW_ACC_OFFSET R W 0h LEGEND R W Read Write R Read only W1toCl Wr...

Page 798: ...T_B R 0h R W 0h 23 22 21 20 19 18 17 16 CFG_ROW_ACC_OFFSET_B R W 0h 15 14 13 12 11 10 9 8 CFG_ROW_ACC_OFFSET_B R W 0h 7 6 5 4 3 2 1 0 CFG_ROW_ACC_OFFSET_B R W 0h LEGEND R W Read Write R Read only W1to...

Page 799: ...W1toCl Write 1 to clear bit n value after reset Table 1 393 SC_M_cfg_sc4 Register Field Descriptions Bit Field Type Reset Description 31 Reserved R 0h 30 28 CFG_NLIN_ACC_INIT_U R W 0h This parameter i...

Page 800: ...CFG_SRC_H R W 0h R 0h R W 0h 7 6 5 4 3 2 1 0 CFG_SRC_H R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 394 SC_M_cfg_sc5 Register Field Descriptions Bit...

Page 801: ...Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 395 SC_M_cfg_sc6 Register Field Descriptions Bit Field Type Reset Description 31 20 Reserved R 0h 19 10 CFG_ROW_ACC_INIT_...

Page 802: ...fter reset Table 1 396 SC_M_cfg_sc8 Register Field Descriptions Bit Field Type Reset Description 31 23 Reserved R 0h 22 12 CFG_NLIN_RIGHT R W 0h This parameter is used by horizontal scaling In anamorp...

Page 803: ...4 3 2 1 0 CFG_LIN_ACC_INC R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 397 SC_M_cfg_sc9 Register Field Descriptions Bit Field Type Reset Descriptio...

Page 804: ...egister 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CFG_NLIN_ACC_INIT R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset...

Page 805: ...3 2 1 0 CFG_NLIN_ACC_INC R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 399 SC_M_cfg_sc11 Register Field Descriptions Bit Field Type Reset Descriptio...

Page 806: ...2 21 20 19 18 17 16 CFG_COL_ACC_OFFSET R W 0h 15 14 13 12 11 10 9 8 CFG_COL_ACC_OFFSET R W 0h 7 6 5 4 3 2 1 0 CFG_COL_ACC_OFFSET R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n...

Page 807: ...0 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved CFG_SC_FACTOR_RAV R 0h R W 0h 7 6 5 4 3 2 1 0 CFG_SC_FACTOR_RAV R W 0h LEGEND R W Read Write R Re...

Page 808: ..._cfg_sc17 Register offset 44h reset 0h SC_M_cfg_sc17 is shown in Figure 1 487 and described in Table 1 402 Figure 1 487 SC_M_cfg_sc17 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Page 809: ..._cfg_sc18 Register offset 48h reset 0h SC_M_cfg_sc18 is shown in Figure 1 488 and described in Table 1 403 Figure 1 488 SC_M_cfg_sc18 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Page 810: ...04 SC_M_cfg_sc19 Register Field Descriptions Bit Field Type Reset Description 31 24 CFG_HPF_COEF3 R W 0h This parameter is used by the peaking block Defines the coefficient 3 of the HPF used in the pe...

Page 811: ...GEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 405 SC_M_cfg_sc20 Register Field Descriptions Bit Field Type Reset Description 31 29 Reserved R 0h 28 20 CFG_NL_...

Page 812: ...19 18 17 16 CFG_NL_LO_SLOPE R W 0h 15 14 13 12 11 10 9 8 Reserved CFG_NL_LO_THR R 0h R W 0h 7 6 5 4 3 2 1 0 CFG_NL_LO_THR R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value a...

Page 813: ...d CFG_NL_HI_SLOPE_SHIFT R 0h R W 0h 15 14 13 12 11 10 9 8 Reserved CFG_NL_HI_THR R 0h R W 0h 7 6 5 4 3 2 1 0 CFG_NL_HI_THR R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value...

Page 814: ..._cfg_sc23 Register offset 5Ch reset 0h SC_M_cfg_sc23 is shown in Figure 1 493 and described in Table 1 408 Figure 1 493 SC_M_cfg_sc23 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Page 815: ...7 26 25 24 Reserved CFG_ORG_W R 0h R W 0h 23 22 21 20 19 18 17 16 CFG_ORG_W R W 0h 15 14 13 12 11 10 9 8 Reserved CFG_ORG_H R 0h R W 0h 7 6 5 4 3 2 1 0 CFG_ORG_H R W 0h LEGEND R W Read Write R Read on...

Page 816: ...OFF_W R 0h R W 0h 23 22 21 20 19 18 17 16 CFG_OFF_W R W 0h 15 14 13 12 11 10 9 8 Reserved CFG_OFF_H R 0h R W 0h 7 6 5 4 3 2 1 0 CFG_OFF_H R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to cle...

Page 817: ...12 17 84h SD_VENC_ectl Encoder Control Section 1 3 12 18 88h SD_VENC_etmg0 Encoder Timing 0 Section 1 3 12 19 8Ch SD_VENC_etmg1 Encoder Timing 1 Section 1 3 12 20 90h SD_VENC_etmg2 Encoder Timing 2 S...

Page 818: ...tion 1 3 12 45 12Ch SD_VENC_l21de Line 21 Data Odd Field Section 1 3 12 46 130h SD_VENC_wss WSS Control Section 1 3 12 47 148h SD_VENC_scctl0 Sub carrier Frequency Control 0 Section 1 3 12 48 14Ch SD_...

Page 819: ...reset 4FFF0000h SD_VENC_pid is shown in Figure 1 496 and described in Table 1 412 Revision Register Figure 1 496 SD_VENC_pid Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 820: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 413 SD_VENC_vmod Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h Reserved 5 DIIV R W 0h Inp...

Page 821: ...ear bit n value after reset Table 1 414 SD_VENC_slave Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 4 FMD R W 0h Field detection mode Effective in slave operation S...

Page 822: ...VENC_size Register 31 30 29 28 27 26 25 24 Reserved VITV R 0h R W 20Dh 23 22 21 20 19 18 17 16 VITV R W 20Dh 15 14 13 12 11 10 9 8 Reserved HITV R 0h R W 6B4h 7 6 5 4 3 2 1 0 HITV R W 6B4h LEGEND R W...

Page 823: ...GP_POL R 0h R W 0h 7 6 5 4 3 2 1 0 Reserved DTV_AVID_POL DTV_FID_POL DTV_VS_POL DTV_HS_POL R 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after...

Page 824: ...1 501 SD_VENC_dtvs0 Register 31 30 29 28 27 26 25 24 Reserved DTV_HS_H_STP R 0h R W 0h 23 22 21 20 19 18 17 16 DTV_HS_H_STP R W 0h 15 14 13 12 11 10 9 8 Reserved DTV_HS_H_STA R 0h R W 0h 7 6 5 4 3 2...

Page 825: ...1 502 SD_VENC_dtvs1 Register 31 30 29 28 27 26 25 24 Reserved DTV_VS_H_STP R 0h R W 0h 23 22 21 20 19 18 17 16 DTV_VS_H_STP R W 0h 15 14 13 12 11 10 9 8 Reserved DTV_VS_H_STA R 0h R W 0h 7 6 5 4 3 2...

Page 826: ...e 1 503 SD_VENC_dtvs2 Register 31 30 29 28 27 26 25 24 Reserved DTV_VS_V_STP R 0h R W 0h 23 22 21 20 19 18 17 16 DTV_VS_V_STP R W 0h 15 14 13 12 11 10 9 8 Reserved DTV_VS_V_STA R 0h R W 0h 7 6 5 4 3 2...

Page 827: ...ribed in Table 1 420 DTV Sync Timing 3 Figure 1 504 SD_VENC_dtvs3 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved DTV_FID_H_STA R 0h...

Page 828: ...6 DTV_FID_V_STA1 R W 0h 15 14 13 12 11 10 9 8 Reserved DTV_FID_F_STA0 DTV_FID_V_STA0 R 0h R W 0h R W 0h 7 6 5 4 3 2 1 0 DTV_FID_V_STA0 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear...

Page 829: ...06 SD_VENC_dtvs5 Register 31 30 29 28 27 26 25 24 Reserved DTV_AVID_H_STP R 0h R W 0h 23 22 21 20 19 18 17 16 DTV_AVID_H_STP R W 0h 15 14 13 12 11 10 9 8 Reserved DTV_AVID_H_STA R 0h R W 0h 7 6 5 4 3...

Page 830: ...tvs6 Register 31 30 29 28 27 26 25 24 Reserved DTV_AVID_V_STP0 R 0h R W 0h 23 22 21 20 19 18 17 16 DTV_AVID_V_STP0 R W 0h 15 14 13 12 11 10 9 8 Reserved DTV_AVID_V_STA0 R 0h R W 0h 7 6 5 4 3 2 1 0 DTV...

Page 831: ...tvs7 Register 31 30 29 28 27 26 25 24 Reserved DTV_AVID_V_STP1 R 0h R W 0h 23 22 21 20 19 18 17 16 DTV_AVID_V_STP1 R W 0h 15 14 13 12 11 10 9 8 Reserved DTV_AVID_V_STA1 R 0h R W 0h 7 6 5 4 3 2 1 0 DTV...

Page 832: ...1 509 SD_VENC_tvdetgp0 Register 31 30 29 28 27 26 25 24 Reserved TVDETGP_H_STP R 0h R W 0h 23 22 21 20 19 18 17 16 TVDETGP_H_STP R W 0h 15 14 13 12 11 10 9 8 Reserved TVDETGP_H_STA R 0h R W 0h 7 6 5 4...

Page 833: ...1 510 SD_VENC_tvdetgp1 Register 31 30 29 28 27 26 25 24 Reserved TVDETGP_V_STP R 0h R W 0h 23 22 21 20 19 18 17 16 TVDETGP_V_STP R W 0h 15 14 13 12 11 10 9 8 Reserved TVDETGP_V_STA R 0h R W 0h 7 6 5...

Page 834: ...iming Figure 1 511 SD_VENC_irq0 Register 31 30 29 28 27 26 25 24 Reserved IRQ_V_STA R 0h R W 0h 23 22 21 20 19 18 17 16 IRQ_V_STA R W 0h 15 14 13 12 11 10 9 8 Reserved IRQ_H_STA R 0h R W 0h 7 6 5 4 3...

Page 835: ...y W1toCl Write 1 to clear bit n value after reset Table 1 428 SD_VENC_estat Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 FIDST R 0h Field ID monitor 3 2 Reserved R...

Page 836: ...h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 429 SD_VENC_ectl Register Field Descriptions Bit Field Type Reset Description 31...

Page 837: ...e 1 514 SD_VENC_etmg0 Register 31 30 29 28 27 26 25 24 Reserved AV_H_STP R 0h R W 694h 23 22 21 20 19 18 17 16 AV_H_STP R W 694h 15 14 13 12 11 10 9 8 Reserved AV_H_STA R 0h R W F4h 7 6 5 4 3 2 1 0 AV...

Page 838: ...VENC_etmg1 Register 31 30 29 28 27 26 25 24 Reserved AV_V_STP0 R 0h R W 207h 23 22 21 20 19 18 17 16 AV_V_STP0 R W 207h 15 14 13 12 11 10 9 8 Reserved AV_V_STA0 R 0h R W 22h 7 6 5 4 3 2 1 0 AV_V_STA0...

Page 839: ...VENC_etmg2 Register 31 30 29 28 27 26 25 24 Reserved AV_V_STP1 R 0h R W 207h 23 22 21 20 19 18 17 16 AV_V_STP1 R W 207h 15 14 13 12 11 10 9 8 Reserved AV_V_STA1 R 0h R W 22h 7 6 5 4 3 2 1 0 AV_V_STA1...

Page 840: ...ming 3 Figure 1 517 SD_VENC_etmg3 Register 31 30 29 28 27 26 25 24 Reserved BST_H_STP R 0h R W D3h 23 22 21 20 19 18 17 16 BST_H_STP R W D3h 15 14 13 12 11 10 9 8 Reserved BST_H_STA R 0h R W 8Fh 7 6 5...

Page 841: ...ng 4 Figure 1 518 SD_VENC_etmg4 Register 31 30 29 28 27 26 25 24 Reserved VBI_H_STP R 0h R W 0h 23 22 21 20 19 18 17 16 VBI_H_STP R W 0h 15 14 13 12 11 10 9 8 Reserved VBI_H_STA R 0h R W 0h 7 6 5 4 3...

Page 842: ...435 CVBS Control 0 Figure 1 519 SD_VENC_cvbs0 Register 31 30 29 28 27 26 25 24 Reserved CSLVL R 0h R W 344h 23 22 21 20 19 18 17 16 CSLVL R W 344h 15 14 13 12 11 10 9 8 Reserved CTLVL R 0h R W BCh 7...

Page 843: ...11 10 9 8 Reserved CYDLY R 0h R W 0h 7 6 5 4 3 2 1 0 Reserved CCM Reserved CLPF YLPF CPSR R 0h R W 0h R 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value a...

Page 844: ...1 521 SD_VENC_ccsc0 Register 31 30 29 28 27 26 25 24 Reserved CCSCB0 R 0h R W 37h 23 22 21 20 19 18 17 16 CCSCB0 R W 37h 15 14 13 12 11 10 9 8 Reserved CCSCA0 R 0h R W 11Dh 7 6 5 4 3 2 1 0 CCSCA0 R W...

Page 845: ...ure 1 522 SD_VENC_ccsc1 Register 31 30 29 28 27 26 25 24 Reserved CCSCD0 R 0h R W 0h 23 22 21 20 19 18 17 16 CCSCD0 R W 0h 15 14 13 12 11 10 9 8 Reserved CCSCC0 R 0h R W 91h 7 6 5 4 3 2 1 0 CCSCC0 R W...

Page 846: ...ibed in Table 1 439 CVBS Color Space Conversion 2 Figure 1 523 SD_VENC_ccsc2 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved CCSCE0...

Page 847: ...1 524 SD_VENC_ccsc3 Register 31 30 29 28 27 26 25 24 Reserved CCSCB1 R 0h R W D3h 23 22 21 20 19 18 17 16 CCSCB1 R W D3h 15 14 13 12 11 10 9 8 Reserved CCSCA1 R 7h R W 1F74h 7 6 5 4 3 2 1 0 CCSCA1 R W...

Page 848: ...1 525 SD_VENC_ccsc4 Register 31 30 29 28 27 26 25 24 Reserved CCSCD1 R 0h R W 0h 23 22 21 20 19 18 17 16 CCSCD1 R W 0h 15 14 13 12 11 10 9 8 Reserved CCSCC1 R 0h R W 1FB9h 7 6 5 4 3 2 1 0 CCSCC1 R W...

Page 849: ...ed in Table 1 442 CVBS Color Space Conversion 5 Figure 1 526 SD_VENC_ccsc5 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved CCSCE1 R...

Page 850: ...27 SD_VENC_ccsc6 Register 31 30 29 28 27 26 25 24 Reserved CCSCB2 R 0h R W 1FD0h 23 22 21 20 19 18 17 16 CCSCB2 R W 1FD0h 15 14 13 12 11 10 9 8 Reserved CCSCA2 R 0h R W 1F06h 7 6 5 4 3 2 1 0 CCSCA2 R...

Page 851: ...re 1 528 SD_VENC_ccsc7 Register 31 30 29 28 27 26 25 24 Reserved CCSCD2 R 0h R W 0h 23 22 21 20 19 18 17 16 CCSCD2 R W 0h 15 14 13 12 11 10 9 8 Reserved CCSCC2 R 0h R W 12Ah 7 6 5 4 3 2 1 0 CCSCC2 R W...

Page 852: ...ed in Table 1 445 CVBS Color Space Conversion 8 Figure 1 529 SD_VENC_ccsc8 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved CCSCE2 R...

Page 853: ...6 CVBS Y Clip Figure 1 530 SD_VENC_cygclp Register 31 30 29 28 27 26 25 24 Reserved CYLCLP R 0h R W 0h 23 22 21 20 19 18 17 16 CYLCLP R W 0h 15 14 13 12 11 10 9 8 Reserved CYUCLP R 0h R W FFFh 7 6 5 4...

Page 854: ...S U Clip Figure 1 531 SD_VENC_cubclp Register 31 30 29 28 27 26 25 24 Reserved CULCLP R 0h R W 1800h 23 22 21 20 19 18 17 16 CULCLP R W 1800h 15 14 13 12 11 10 9 8 Reserved CUUCLP R 0h R W 7FFh 7 6 5...

Page 855: ...S V Clip Figure 1 532 SD_VENC_cvrclp Register 31 30 29 28 27 26 25 24 Reserved CVLCLP R 0h R W 1800h 23 22 21 20 19 18 17 16 CVLCLP R W 1800h 15 14 13 12 11 10 9 8 Reserved CVUCLP R 0h R W 7FFh 7 6 5...

Page 856: ...ent 0 Figure 1 533 SD_VENC_ylpf0 Register 31 30 29 28 27 26 25 24 YLPFC3 R W 0h 23 22 21 20 19 18 17 16 YLPFC2 R W 0h 15 14 13 12 11 10 9 8 YLPFC1 R W 0h 7 6 5 4 3 2 1 0 YLPFC0 R W 0h LEGEND R W Read...

Page 857: ...d in Table 1 450 CVBS Luma LPF Coefficient 1 Figure 1 534 SD_VENC_ylpf1 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 YLPFC5 R W 40h 7 6 5...

Page 858: ...ent 0 Figure 1 535 SD_VENC_clpf0 Register 31 30 29 28 27 26 25 24 CLPFC3 R W Ch 23 22 21 20 19 18 17 16 CLPFC2 R W 0h 15 14 13 12 11 10 9 8 CLPFC1 R W 0h 7 6 5 4 3 2 1 0 CLPFC0 R W 0h LEGEND R W Read...

Page 859: ...n Table 1 452 CVBS Chroma LPF Coefficient 1 Figure 1 536 SD_VENC_clpf1 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 CLPFC5 R W 28h 7 6 5 4...

Page 860: ...VENC_upf0 Register 31 30 29 28 27 26 25 24 UPFC3 R W 0h 23 22 21 20 19 18 17 16 UPFC2 R W 0h 15 14 13 12 11 10 9 8 UPFC1 R W 0h 7 6 5 4 3 2 1 0 UPFC0 R W 0h LEGEND R W Read Write R Read only W1toCl Wr...

Page 861: ...nt 1 Figure 1 538 SD_VENC_upf1 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 UPFC6 R W 4Eh 15 14 13 12 11 10 9 8 UPFC5 R W ECh 7 6 5 4 3 2 1 0 UPFC4 R W 6h LEGEND R W Read Wri...

Page 862: ...e R Read only W1toCl Write 1 to clear bit n value after reset Table 1 455 SD_VENC_l21ctl Register Field Descriptions Bit Field Type Reset Description 31 16 Reserved R 0h 15 8 L21DF R W 0h Closed capti...

Page 863: ...25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 L21DO0 R W 0h 7 6 5 4 3 2 1 0 L21DO1 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after...

Page 864: ...24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 L21DE0 R W 0h 7 6 5 4 3 2 1 0 L21DE1 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after re...

Page 865: ...EN Reserved R 0h R W 0h R 0h 23 22 21 20 19 18 17 16 Reserved WSS_DATA R 0h R W 0h 15 14 13 12 11 10 9 8 WSS_DATA R W 0h 7 6 5 4 3 2 1 0 WSS_DATA R W 0h LEGEND R W Read Write R Read only W1toCl Write...

Page 866: ...Figure 1 543 SD_VENC_scctl0 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 SCP0 R W 87h 15 14 13 12 11 10 9 8 Reserved SCSD R 0h R W 0h 7 6 5 4 3 2 1 0 SCSD R W 0h LEGEND R W...

Page 867: ...arrier Frequency Control 1 Figure 1 544 SD_VENC_scctl1 Register 31 30 29 28 27 26 25 24 SCP2 R W 21h 23 22 21 20 19 18 17 16 SCP2 R W 21h 15 14 13 12 11 10 9 8 SCP1 R W 19h 7 6 5 4 3 2 1 0 SCP1 R W 19...

Page 868: ...0 29 28 27 26 25 24 Reserved DA1E DA0E R 0h R W 0h R W 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 DA1S DA0S R W 0h R W 0h LEGEND R W Read Write R Read...

Page 869: ...27 26 25 24 DUPFC3 R W 0h 23 22 21 20 19 18 17 16 DUPFC2 R W 0h 15 14 13 12 11 10 9 8 DUPFC1 R W 0h 7 6 5 4 3 2 1 0 DUPFC0 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value...

Page 870: ..._dupf1 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 DUPFC6 R W 4Eh 15 14 13 12 11 10 9 8 DUPFC5 R W ECh 7 6 5 4 3 2 1 0 DUPFC4 R W 6h LEGEND R W Read Write R Read only W1toCl...

Page 871: ...17 16 Reserved DAIV DADC R 0h R W 0h R W 0h 15 14 13 12 11 10 9 8 Reserved DALVL R 0h R W 0h 7 6 5 4 3 2 1 0 DALVL R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after re...

Page 872: ...is shown in Figure 1 549 and described in Table 1 465 Internal Test Register Figure 1 549 SD_VENC_vtest Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 V...

Page 873: ...COMP Main Register 1 Section 1 3 13 1 4h VCOMP_reg1 VCOMP Main Register 2 Section 1 3 13 2 8h VCOMP_reg2 VCOMP Main Register 3 Section 1 3 13 3 Ch VCOMP_reg3 VCOMP Aux Register 1 Section 1 3 13 4 10h...

Page 874: ...E_NUMPIX_PER_LINE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 467 VCOMP_reg0 Register Field Descriptions Bit Field Type Reset Description 31 CFG_MA...

Page 875: ...e NF and pixel data to the downstream module is not sent This mode forces the VCOMP to request pictures from the upstream modules Thus these modules like the DEI can go ahead and load up with one or m...

Page 876: ...SE_NUMLINES R 0h R W 0h 7 6 5 4 3 2 1 0 CFG_MAIN_USE_NUMLINES R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 469 VCOMP_reg2 Register Field Description...

Page 877: ...TIVE_NUMPIX_PER_LINE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 470 VCOMP_reg3 Register Field Descriptions Bit Field Type Reset Description 31 CFG...

Page 878: ...e NF and pixel data to the downstream module is not sent This mode forces the VCOMP to request pictures from the upstream modules Thus these modules like the DEI can go ahead and load up with one or m...

Page 879: ...USE_NUMLINES R 0h R W 0h 7 6 5 4 3 2 1 0 CFG_AUX_USE_NUMLINES R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 472 VCOMP_reg5 Register Field Description...

Page 880: ...MLINES R 0h R W 0h 23 22 21 20 19 18 17 16 CFG_DSPLY_NUMLINES R W 0h 15 14 13 12 11 10 9 8 Reserved CFG_DSPLY_NUMPIX_PER_LINE R 0h R W 0h 7 6 5 4 3 2 1 0 CFG_DSPLY_NUMPIX_PER_LINE R W 0h LEGEND R W Re...

Page 881: ..._MAIN_X_ORIGIN R 0h R W 0h 7 6 5 4 3 2 1 0 CFG_DSPLAY_MAIN_X_ORIGIN R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 474 VCOMP_reg7 Register Field Descr...

Page 882: ...ource FID bit 0 out of the VCOMP is the inverse of the respective bit from the Upstream Module 10 Source FID bit 0 out of the VCOMP is 0 11 Source FID bit 0 out of the VCOMP is 1 When both the Main an...

Page 883: ...D_CB_VAL CFG_DSPLY_BCKGRND_Y_VAL R W 0h R W 0h 7 6 5 4 3 2 1 0 CFG_DSPLY_BCKGRND_Y_VAL R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 476 VCOMP_reg9 R...

Page 884: ...Write 1 to clear bit n value after reset Table 1 477 VCOMP_reg10 Register Field Descriptions Bit Field Type Reset Description 31 0 CFG_DSPLY_TIMEOUT_ COUNT R W 0h Timeout counter in DSS system clock c...

Page 885: ...LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 478 VCOMP_reg11 Register Field Descriptions Bit Field Type Reset Description 31 30 CFG_NF_HANDLING R W 0h 00...

Page 886: ...same as the respective bit from the Upstream Module 01 Encoder FID bit 1 out of the VCOMP is the inverse of the respective bit from the Upstream Module 10 Encoder FID bit 1 out of the VCOMP is 0 11 E...

Page 887: ..._PARSER_output_port_b_enc_ fid Current and Previous Output Port B Encoder FID values Section 1 3 14 12 30h VIP_PARSER_output_port_a_src0 _size Width and Height for Source 0 Section 1 3 14 13 34h VIP_P...

Page 888: ...ize Width and Height for Source 12 Section 1 3 14 41 A4h VIP_PARSER_output_port_b_src1 3_size Width and Height for Source 13 Section 1 3 14 42 A8h VIP_PARSER_output_port_b_src1 4_size Width and Height...

Page 889: ...rved R 0h 5 CLIP_ACTIVE R W 0h Discrete Sync Only 0 Do not clip active pixels 1 Clip Active Pixels as follows 0xFF andgt 0xFE 0x00 andgt 0x01 4 CLIP_BLNK R W 0h Discrete Sync Only 0 Do not clip Blanki...

Page 890: ...3 2 1 0 CLR_ASYNC_FIFO_ RD CLR_ASYNC_FIFO_ WR CTRL_CHAN_SEL SYNC_TYPE R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 482 VIP_PAR...

Page 891: ...allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active In basic discrete...

Page 892: ...ata 23 16 the G channel is on 15 8 and the B channel is on data 7 0 00 Use data 7 0 to extract control codes 01 Use data 15 8 to extract control codes 10 Use data 23 16 to extract control codes 11 Und...

Page 893: ...tions Bit Field Type Reset Description 31 27 Reserved R 0h 26 16 SRC0_NUMPIX R W 0h Number of expected pixels on Source Number 0 The Port_a_src0_size interrupt will trigger if a line is encountered th...

Page 894: ...3 2 1 0 CLR_ASYNC_FIFO_ RD CLR_ASYNC_FIFO_ WR CTRL_CHAN_SEL SYNC_TYPE R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 484 VIP_PAR...

Page 895: ...allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active In basic discrete...

Page 896: ...FIFO_WR R W 0h 0 Normal 1 Clear Async FIFO Write Logic 5 4 CTRL_CHAN_SEL R W 0h PORT B supports on 8b mode Always write 0 to this field The anc_chan_sel_8b register is used to select the Luma or Chrom...

Page 897: ...t Table 1 485 VIP_PARSER_xtra_port_b Register Field Descriptions Bit Field Type Reset Description 31 27 Reserved R 0h 26 16 SRC0_NUMPIX R W 0h Number of expected pixels on Source Number 0 The Port_b_s...

Page 898: ..._VDET_MASK R W 0h R W 0h R 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 486 VIP_PARSER_fiq_mask Register Field Descri...

Page 899: ...P_PARSER_fiq_mask Register Field Descriptions continued Bit Field Type Reset Description 5 Reserved R 0h 4 OUTPUT_FIFO_PRTA_Y UV_OF R W 0h Output FIFO Port A Luma Overflow Mask 3 ASYNC_FIFO_PRTB_OF R...

Page 900: ...escription 31 22 Reserved R 0h 21 PORT_B_CFG_DISABLE _COMPLETE_CLR R W 0h Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ 20 PORT_A_CFG_DISABLE _COMPLETE_CLR R W 0h Write 1 followed by...

Page 901: ...d Type Reset Description 4 OUTPUT_FIFO_PRTA_Y UV_CLR R W 0h Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ 3 ASYNC_FIFO_PRTB_CL R R W 0h Write 1 followed by 0 to Clear Async FIFO...

Page 902: ..._PRT A_LUMA_STATUS ASYNC_FIFO_PRTB_ STATUS ASYNC_FIFO_PRTA_ STATUS PRTB_VDET_STATU S PRTA_VDET_STATU S R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear...

Page 903: ...L UMA_STATUS R 0h Output FIFO Port B Luma Overflow Status 6 OUTPUT_FIFO_PRTA_A NC_STATUS R 0h Output FIFO Port A Ancillary Overflow Status 5 OUTPUT_FIFO_PRTA_C HROMA_STATUS R 0h Output FIFO Port A Chr...

Page 904: ...0_PREV_ SOURCE_FID R 1h R 1h R 1h R 1h R 1h R 1h R 1h R 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 489 VIP_PARSER_output_port_a_src_fid Register Field...

Page 905: ...for Current Field 10 PRTA_SRC5_PREV_SO URCE_FID R 1h For Source ID 5 from Port A Source Field ID for Previous Field 9 PRTA_SRC4_CURR_SO URCE_FID R 1h For Source ID 4 from Port A Source Field ID for Cu...

Page 906: ...h R 1h R 1h R 1h R 1h R 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 490 VIP_PARSER_output_port_a_enc_fid Register Field Descriptions Bit Field Type Res...

Page 907: ...d ID for Current Field 10 PRTA_SRC5_PREV_ENC _FID R 1h For Source ID 5 from Port A Encoder Field ID for Previous Field 9 PRTA_SRC4_CURR_EN C_FID R 1h For Source ID 4 from Port A Encoder Field ID for C...

Page 908: ...C0_PREV_ SOURCE_FID R 1h R 1h R 1h R 1h R 1h R 1h R 1h R 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 491 VIP_PARSER_output_port_b_src_fid Register Fiel...

Page 909: ...for Current Field 10 PRTB_SRC5_PREV_SO URCE_FID R 1h For Source ID 5 from Port B Source Field ID for Previous Field 9 PRTB_SRC4_CURR_SO URCE_FID R 1h For Source ID 4 from Port B Source Field ID for Cu...

Page 910: ...h R 1h R 1h R 1h R 1h R 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 492 VIP_PARSER_output_port_b_enc_fid Register Field Descriptions Bit Field Type Res...

Page 911: ...d ID for Current Field 10 PRTB_SRC5_PREV_ENC _FID R 1h For Source ID 5 from Port B Encoder Field ID for Previous Field 9 PRTB_SRC4_CURR_EN C_FID R 1h For Source ID 4 from Port B Encoder Field ID for C...

Page 912: ...1 575 VIP_PARSER_output_port_a_src0_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC0_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC0_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC0_HEIGH...

Page 913: ...1 576 VIP_PARSER_output_port_a_src1_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC1_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC1_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC1_HEIGH...

Page 914: ...1 577 VIP_PARSER_output_port_a_src2_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC2_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC2_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC2_HEIGH...

Page 915: ...1 578 VIP_PARSER_output_port_a_src3_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC3_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC3_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC3_HEIGH...

Page 916: ...1 579 VIP_PARSER_output_port_a_src4_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC4_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC4_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC4_HEIGH...

Page 917: ...1 580 VIP_PARSER_output_port_a_src5_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC5_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC5_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC5_HEIGH...

Page 918: ...1 581 VIP_PARSER_output_port_a_src6_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC6_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC6_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC6_HEIGH...

Page 919: ...1 582 VIP_PARSER_output_port_a_src7_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC7_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC7_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC7_HEIGH...

Page 920: ...1 583 VIP_PARSER_output_port_a_src8_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC8_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC8_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC8_HEIGH...

Page 921: ...1 584 VIP_PARSER_output_port_a_src9_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC9_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC9_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC9_HEIGH...

Page 922: ...85 VIP_PARSER_output_port_a_src10_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC10_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC10_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC10_HEIG...

Page 923: ...86 VIP_PARSER_output_port_a_src11_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC11_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC11_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC11_HEIG...

Page 924: ...87 VIP_PARSER_output_port_a_src12_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC12_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC12_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC12_HEIG...

Page 925: ...88 VIP_PARSER_output_port_a_src13_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC13_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC13_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC13_HEIG...

Page 926: ...89 VIP_PARSER_output_port_a_src14_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC14_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC14_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC14_HEIG...

Page 927: ...90 VIP_PARSER_output_port_a_src15_size Register 31 30 29 28 27 26 25 24 Reserved PRTA_SRC15_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTA_SRC15_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTA_SRC15_HEIG...

Page 928: ...1 591 VIP_PARSER_output_port_b_src0_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC0_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC0_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC0_HEIGH...

Page 929: ...1 592 VIP_PARSER_output_port_b_src1_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC1_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC1_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC1_HEIGH...

Page 930: ...1 593 VIP_PARSER_output_port_b_src2_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC2_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC2_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC2_HEIGH...

Page 931: ...1 594 VIP_PARSER_output_port_b_src3_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC3_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC3_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC3_HEIGH...

Page 932: ...1 595 VIP_PARSER_output_port_b_src4_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC4_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC4_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC4_HEIGH...

Page 933: ...1 596 VIP_PARSER_output_port_b_src5_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC5_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC5_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC5_HEIGH...

Page 934: ...1 597 VIP_PARSER_output_port_b_src6_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC6_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC6_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC6_HEIGH...

Page 935: ...1 598 VIP_PARSER_output_port_b_src7_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC7_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC7_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC7_HEIGH...

Page 936: ...1 599 VIP_PARSER_output_port_b_src8_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC8_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC8_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC8_HEIGH...

Page 937: ...1 600 VIP_PARSER_output_port_b_src9_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC9_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC9_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC9_HEIGH...

Page 938: ...01 VIP_PARSER_output_port_b_src10_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC10_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC10_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC10_HEIG...

Page 939: ...02 VIP_PARSER_output_port_b_src11_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC11_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC11_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC11_HEIG...

Page 940: ...03 VIP_PARSER_output_port_b_src12_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC12_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC12_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC12_HEIG...

Page 941: ...04 VIP_PARSER_output_port_b_src13_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC13_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC13_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC13_HEIG...

Page 942: ...05 VIP_PARSER_output_port_b_src14_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC14_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC14_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC14_HEIG...

Page 943: ...06 VIP_PARSER_output_port_b_src15_size Register 31 30 29 28 27 26 25 24 Reserved PRTB_SRC15_WIDTH R 0h R 0h 23 22 21 20 19 18 17 16 PRTB_SRC15_WIDTH R 0h 15 14 13 12 11 10 9 8 Reserved PRTB_SRC15_HEIG...

Page 944: ...he VDET bit setting for Line Mux Mode Figure 1 607 VIP_PARSER_port_a_vdet_vec Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRTA_VDET_VEC R 0h LEGEND R...

Page 945: ...he VDET bit setting for Line Mux Mode Figure 1 608 VIP_PARSER_port_b_vdet_vec Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRTB_VDET_VEC R 0h LEGEND R...

Page 946: ...BYPASS_N Reserved ANC_SKIP_NUMPIX R W 0h R 0h R W 0h 7 6 5 4 3 2 1 0 ANC_SKIP_NUMPIX R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 527 VIP_PARSER_xtr...

Page 947: ...h 23 22 21 20 19 18 17 16 ANC_USE_NUMLINES R W 0h 15 14 13 12 11 10 9 8 Reserved ANC_SKIP_NUMLINES R 0h R W 0h 7 6 5 4 3 2 1 0 ANC_SKIP_NUMLINES R W 0h LEGEND R W Read Write R Read only W1toCl Write 1...

Page 948: ...T_BYPASS_N Reserved ACT_SKIP_NUMPIX R W 0h R 0h R W 0h 7 6 5 4 3 2 1 0 ACT_SKIP_NUMPIX R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 529 VIP_PARSER_x...

Page 949: ...W 0h 23 22 21 20 19 18 17 16 ACT_USE_NUMLINES R W 0h 15 14 13 12 11 10 9 8 Reserved ACT_SKIP_NUMLINES R 0h R W 0h 7 6 5 4 3 2 1 0 ACT_SKIP_NUMLINES R W 0h LEGEND R W Read Write R Read only W1toCl Wri...

Page 950: ...BYPASS_N Reserved ANC_SKIP_NUMPIX R W 0h R 0h R W 0h 7 6 5 4 3 2 1 0 ANC_SKIP_NUMPIX R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 531 VIP_PARSER_xtr...

Page 951: ...h 23 22 21 20 19 18 17 16 ANC_USE_NUMLINES R W 0h 15 14 13 12 11 10 9 8 Reserved ANC_SKIP_NUMLINES R 0h R W 0h 7 6 5 4 3 2 1 0 ANC_SKIP_NUMLINES R W 0h LEGEND R W Read Write R Read only W1toCl Write 1...

Page 952: ...T_BYPASS_N Reserved ACT_SKIP_NUMPIX R W 0h R 0h R W 0h 7 6 5 4 3 2 1 0 ACT_SKIP_NUMPIX R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 1 533 VIP_PARSER_x...

Page 953: ...W 0h 23 22 21 20 19 18 17 16 ACT_USE_NUMLINES R W 0h 15 14 13 12 11 10 9 8 Reserved ACT_SKIP_NUMLINES R 0h R W 0h 7 6 5 4 3 2 1 0 ACT_SKIP_NUMLINES R W 0h LEGEND R W Read Write R Read only W1toCl Wri...

Page 954: ...line mux mode going to the VPDMA For example bit 0 is srcnum 0 bit 1 is srcnum 1 etc A 0 in a bit position means that the hardware will wait for that srcnum if it is in the middle of a frame to contin...

Page 955: ...TI line mux mode going to the VPDMA For example bit 0 is srcnum 0 bit 1 is srcnum 1 etc A 0 in a bit position means that the hardware will wait for that srcnum if it is in the middle of a frame to co...

Page 956: ...sponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related inf...

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