Texas Instruments DAC8574 User Manual Download Page 32

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13-Jun-2003

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Revision History

REV

ECN Number

Approved

DAC8534 RevA.Sch

DOCUMENTCONTROL #

0.1µF

+5VA

SCLK

10K

VSS

Op Amp

VCC

C10

1µF

R12
10K

C12

1nF

GND

TRIM

TEMP

OUT

V+

REF02AU(8)

C11

10µF

0.1µF

VCC

TP1

TP2

EXTERNAL

REFERENCE

R11

100K

R10

20K

VCC

VDD

OUTPUT HEADER

VrefH

FSX

10µF

DAC8534_74 EVM

J. PARGUIAN

W10

VSS

+REFin

Tantalum

SDI

CLKX

CLKR

FSR

VoutB

IO_V/DVDD

A3/LDAC

GND

VrefH

VrefL

VoutA

A2/EN

VoutD

SDA/Din

SCL/SCLK

LDAC/SYNC

AVDD

VoutC

DAC7574/8534/8574

VDD

R15 440/0

R16 440/0

10K

-REFin

OUT_A1

OUT_C1

OUT_B1

OUT_D1

OUT_A2

OUT_B2

OUT_C2

OUT_D2

OUT_A

OUT_B

OUT_C

OUT_D

U8A
OPA2227UA

U8B

OPA2227UA

R17
0

TP5

-REFin

VrefH

R14

10K

VCC

0.1µF

TP3

VOUT

U2_+IN

U2_-IN

U2_OUT

VrefL

11 12

13 14

15 16

Serial Header

VrefL

TP4

R23

R22

R21

R20

R24

C13

R19

R18

VCC = +15V Analog
VDD = +2.7V to +5.0V Digital
VSS = 0V to -15V Analog

TP6

+Vin

TP7

-Vin

+5VA

NOTE: Voltage range of -REFin input should not exceed
0 - VrefH.

VCC

VSS

+5VA

-5VA

VDD

+3.3VD+1.8VD

+3.3VA

GPIO0

GPIO1

SCL

SDA

R25

R26

GPIO2

GPIO3

GPIO0

GPIO1

GPIO2

GPIO3

R27

R28

GPIO4

GPIO5

GPIO4

GPIO5

R31

R32

R33

R29

0
R30
0

FSX

GPIO0

(LDAC)

(SYNC)

(A3)

(EN)

(A2)

(A1)

(A0)

(LDAC)

(A3)
(EN)

(A2)
(A1)

(A0)

R34

0
R35

SCLK

SDI

R36

R37

CLKX

R38

R39

+3.3VA

AVDD

W11

W12

W13

6447711

R13

100

W15

Summary of Contents for DAC8574

Page 1: ...DAC8574 Evaluation Module June 2003 Data Acquisition Digital Analog Converters User s Guide SLAU109 ...

Page 2: ...titute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction ...

Page 3: ... handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR A...

Page 4: ...here is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 60 C The EVM is designed to operate properly with certain components above 60 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors ...

Page 5: ...nual This document contains the following chapters Chapter 1 EVM Overview Chapter 2 PCB Design and Performance Chapter 3 EVM Operation Information About Cautions and Warnings This book may contain cautions and warnings The information in a caution or a warning is provided for your protection Read each caution and warning carefully This is an example of a caution statement A caution statement descr...

Page 6: ... mail the Data Converter Application Team at dataconvapps list ti com Inlcude in the subject heading the product you have questions or concerns with FCC Warning This equipment is intended for use in a laboratory test environment only It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 ...

Page 7: ...mance 2 1 2 1 PCB Layout 2 2 2 2 EVM Performance 2 6 2 3 Bill of Materials 2 11 3 EVM Operation 3 1 3 1 Factory Default Setting 3 2 3 2 Host Processor Interface 3 2 3 3 EVM Stacking 3 3 3 4 The Output Op Amp 3 3 3 4 1 Unity Gain Output 3 4 3 4 2 Output Gain of Two 3 4 3 4 3 Capacitive Load Drive 3 4 3 5 Optional Signal Conditioning Op Amp U8B 3 5 3 6 Jumper Setting 3 6 3 7 Schematic 3 7 ...

Page 8: ... 2 6 2 9 INL and DNL Characterization Graph of DAC A 2 7 2 10 INL and DNL Characterization Graph of DAC B 2 8 2 11 INL and DNL Characterization Graph of DAC C 2 9 2 12 INL and DNL Characterization Graph of DAC D 2 10 Tables 2 1 Parts List 2 11 3 1 Factory Default Jumper Setting 3 2 3 2 DAC Output Channel Mapping 3 3 3 3 Unity Gain Output Jumper Settings 3 4 3 4 Gain of Two Output Jumper Settings 3...

Page 9: ...apter gives a general overview of the DAC8574 evaluation module EVM and describes some of the factors that must be considered in using this module Topic Page 1 1 Features 1 2 1 2 Power Requirements 1 2 1 3 EVM Basic Functions 1 3 Chapter 1 ...

Page 10: ...ctively or through J6 1 and J6 2 terminals The 5 VA connects through J5 3 or J6 3 and the 3 3 VA connects through J6 8 All of the analog power supplies are referenced to analog ground through J1 2 and J6 6 terminals The device under test U1 analog power supply can be powered by either 5 VA or 3 3 VA by selecting the proper position of jumper W1 This allows the DAC8574 analog section to operate in ...

Page 11: ...SP or some sort of a waveform generator The headers J2 and P2 are the connectors provided to allow the control signals and data required to interface a host processor or waveform generator to the DAC8574 EVM using a custom built cable A specific adapter interface card is also available for most of TI s DSP starter kit DSK and the card model depend on the type of the TI DSP starter kit to be used M...

Page 12: ... 1 EVM Block Diagram DAC Module Output Buffer Module VCC VSS VCC GND GND VDD DAC Out 4 CH J1 J5 J6 P6 External Reference Module VDD J2 P2 A0 A1 LDAC SCL SDA TP2 W4 TP1 VSS W2 W11 W12 W13 J4 P4 8 CH TP3 A2 A0 A2 TP5 W6 W9 W7 W3 W15 W5 VSS VREFH VREFL VREFH 3 3 VA 5 VA A3 A1 W8 A3 W10 ...

Page 13: ...and mechanical characteristics of the EVM This section also shows the resulting performance of the EVM which can be compared to the device specification listed in the data sheet The list of components used on the module is also included in this section Topic Page 2 1 PCB Layout 2 2 2 2 EVM Performance 2 6 2 3 Bill of Materials 2 11 Chapter 2 ...

Page 14: ...d plane is very important and must be carefully considered in the layout process A solid plane is ideally preferred but sometimes impractical so when solid planes are not possible a split plane can do the job as well When considering a split plane design analyze the component placement and carefully split the board into its analog and digital sections starting from the device under test The ground...

Page 15: ...PCB Layout 2 3 PCB Design and Performance Figure 2 1 Top Silkscreen Figure 2 2 Layer 1 Top Signal Plane Figure 2 3 Layer 2 Ground Plane ...

Page 16: ...PCB Layout 2 4 Figure 2 4 Layer 3 Power Plane Figure 2 5 Layer 4 Bottom Signal Plane Figure 2 6 Bottom Silkscreen ...

Page 17: ...PCB Layout 2 5 PCB Design and Performance Figure 2 7 Drill Drawing ...

Page 18: ... The EVM board is tested for all codes of 65535 and the device under test DUT is allowed to settle for 1ms before the meter is read This process is repeated for all codes to generate the measurements for INL and DNL results and is shown in Figure 2 9 The parameters and results of the DAC8574 EVM characterization test can be seen in Figure 2 8 Figure 2 8 DAC8574 EVM Test Parameters and Results ...

Page 19: ...EVM Performance 2 7 PCB Design and Performance Figure 2 9 INL and DNL Characterization Graph of DAC A ...

Page 20: ...EVM Performance 2 8 Figure 2 10 INL and DNL Characterization Graph of DAC B ...

Page 21: ...EVM Performance 2 9 PCB Design and Performance Figure 2 11 INL and DNL Characterization Graph of DAC C ...

Page 22: ...EVM Performance 2 10 Figure 2 12 INL and DNL Characterization Graph of DAC D ...

Page 23: ...00 kΩ BOURNS_32X4W Series 5T Pot 13 1 J6 Samtec TSM 105 01 T DV 5X2X0 1 10 pin 3A isolated power socket 14 2 J2 J4 Samtec TSM 110 01 S DV M 10X2X 1 20 pin 0 025 sq SMT socket 15 2 J1 J5 On Shore Technology ED555 3DS 3 Pin terminal connector 16 1 U1 Texas Instruments DAC8574IPW 16 Bit quad voltage output serial input I2C DAC TSSOP 16 17 1 U2 Texas Instruments OPA627AU 8 SOP D precision op amp 18 1 ...

Page 24: ...2 12 ...

Page 25: ...er to the DAC8574 data sheet SLAS377A for information about its serial interface and other related topics The EVM board is factory tested and configured to operate in the bipolar output mode Topic Page 3 1 Factory Default Setting 3 2 3 2 Host Processor Interface 3 2 3 3 EVM Stacking 3 3 3 4 The Output Op Amp 3 3 3 5 Optional Signal Conditioning Op Amp U8B 3 5 3 6 Jumper Setting 3 6 3 7 Schematic 3...

Page 26: ...ain of 2 J4 1 2 DAC output A VOUTA is connected to the noninverting input of the output op amp U2 3 2 Host Processor Interface The host processor basically drives the DAC so the DAC s proper operation depends on the successful configuration between the host processor and the EVM board In addition a properly written code is also required to operate the DAC A custom cable can be made specific to the...

Page 27: ...ust have its own unique I2C address This is accomplished by configuring the address jumpers W7 through W10 refer to the data sheet for I2C addressing The LDAC signal can be shared to have a synchronous DAC output update and is hardware driven by GPIO0 If controlling the LDAC through software is desired the GPIO0 signal must be set low through software or the J2 pin 2 can be pin strapped to DGND 3 ...

Page 28: ... the jumpers W3 and W15 These configurations allow the user to choose whether the DAC output has VREFH as an offset or not Table 3 4 shows the proper jumper settings of the EVM for the 2 gain output of the DAC Table 3 4 Gain of Two Output Jumper Settings Jumper Setting Reference Unipolar Bipolar Function Close Close Inverting input of the output op amp U2 is connected to VREFH for use as its offse...

Page 29: ...1 of W15 jumper and maybe used as the output terminal 3 5 Optional Signal Conditioning Op Amp U8B One part of the dual package op amp OPA2132 U8 is used for reference buffering U8A while the other is unused This unused op amp U8B is left for whatever op amp circuit application the user desires to implement The 1206 footprint for the resistors and capacitors surrounding the U8B op amp are not popul...

Page 30: ...4 1 3 Negative supply rail of the output op amp U2 is powered by VSS for bipolar operation W5 1 3 Negative supply rail of the output op amp U2 is tied to AGND for unipolar operation 1 3 VREFL is tied to AGND W6 1 3 Routes the user supplied negative reference from TP2 or J4 18 to the VREFL input of the DAC8574 This voltage should be within the range of 0V to VREFH A0 pin is set high through pullup ...

Page 31: ...Routes VOUTD to J4 8 W13 1 3 Routes VOUTD to J4 16 Disconnects the inverting input of the output op amp U2 from AGND W15 Connects the inverting input of the output op amp U2 to AGND for gain of 2 Legend Indicates the corresponding pins that are shorted or closed 3 7 Schematic The schematic is located on the following page ...

Page 32: ...DAC SYNC 9 AVDD 4 VoutC 7 U1 DAC7574 8534 8574 VDD R15 440 0 R16 440 0 R5 3K R7 3K R1 10K R2 10K R3 10K R4 10K REFin W2 OUT_A1 OUT_C1 OUT_B1 OUT_D1 OUT_A2 OUT_B2 OUT_C2 OUT_D2 OUT_A OUT_B OUT_C OUT_D 2 3 1 8 4 U8A OPA2227UA 5 6 7 U8B OPA2227UA R17 0 TP5 REFin VrefH R14 10K VrefH VCC C7 0 1µF TP3 VOUT U2_ IN U2_ IN U2_OUT VrefL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 17 19 18 J2 Serial Header W6 ...

Page 33: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments DAC8574EVM ...

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