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Texas Instruments DAC63204EVM User Manual Download Page 16

BOOSTXL-DAC-PORT Interface Left

BOOSTXL-DAC-PORT Interface Right

5

4

1
2
3

6
7
8
9
10
11
12
13
14
15
16

J2

5

4

1

2
3

6
7
8
9

10

11

12
13
14
15
16

J1

Pull ups for all digital IOs

DAC63204RTER

VDD

15

FB0

12

FB1

9

FB2

4

FB3

1

OUT0

11

OUT1

10

OUT2

3

OUT3

2

A0/SDI

7

CAP

13

EP

17

GPIO/SDO

5

SCL/SYNC

6

SDA/SCLK

8

VREF

16

AGND

14

U1

DAC_GPIO/SDO
DAC_SCL/SYNC
DAC_A0/SDI
DAC_SDA/SCLK

DAC_VREF

DAC_CAP

GND

DAC_FB0

DAC_FB1

3.32k

R1

3.32k

R2

3.32k

R3

3.32k

R4

DAC_VDD

GND

DAC_VREF

100nF
50V

C2

GND

DAC_VDD

1µF

C3

GND

100nF
50V

C4

GND

DAC_CAP

GND

Reference and Decoupling Capacitors for DAC

DAC_VDD

0

R5

0

R6

0

R7

0

R8

DAC_OUT0

DAC_OUT1

GND

DAC_SCLK
DAC_SDO
DAC_SCL
EXT_REF

DAC_SDI
DAC_SYNC
DAC_SDA

DAC_GPIO

0

R13

0

R15

DAC_GPIO/SDO

DAC_GPIO

DAC_SDO

0

R17

0

R19

DAC_SCL/SYNC

DAC_SCL

DAC_SYNC

0

R14

0

R16

DAC_A0/SDI

DAC_A0

DAC_SDI

0

R18

0

R20

DAC_SDA/SCLK

DAC_SDA

DAC_SCLK

10.0k

R10

DNP

10.0k

R12

DNP

GND

DAC_VDD

DAC_A0

Interface selection I2C / SPI

100nF
50V

C1

2.2µF
10V

C5

10.0k

R1

1

DNP

GND

0

R9

EXT_REF

DAC_VREF

GND

DAC configured for Voltage outputs

DAC_VREF
DAC_CAP

DAC_VREF

DAC_SDO

USB_VBUS

DAC_SCL

DAC_SDI

DAC_SDA

DAC_SCLK

DAC_SYNC

DAC_VDD

DAC_VDD

1

2

J3

SH-J1

3.32k

R25

DAC_VDD

DAC_FB2

DAC_FB3

DAC_OUT2

DAC_OUT3

DAC_FB0
DAC_OUT0
DAC_OUT1
DAC_FB1

DAC_FB3
DAC_OUT3

DAC_FB2

DAC_OUT2

FTDI_GPIO3

DAC_GPIO

Figure 4-2. DAC63204EVM Schematic Page 2

Schematic, PCB Layout, and Bill of Materials

www.ti.com

16

DAC63204EVM User's Guide

SLAU866 – NOVEMBER 2021

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Copyright © 2021 Texas Instruments Incorporated

Summary of Contents for DAC63204EVM

Page 1: ...AC43204 DACx3204 commercial buffered voltage output DACs in a variety of configurations Throughout this document the terms evaluation board evaluation module and EVM are synonymous with the DAC63204EVM This document includes a schematic printed circuit board PCB layouts and a complete bill of materials www ti com SLAU866 NOVEMBER 2021 Submit Document Feedback DAC63204EVM User s Guide 1 Copyright 2...

Page 2: ... Configuration Page 14 Figure 3 9 Low Level Configuration Page Options 14 Figure 4 1 DAC63204EVM Schematic Page 1 15 Figure 4 2 DAC63204EVM Schematic Page 2 16 Figure 4 3 DAC63204EVM PCB Components Layout 17 Figure 4 4 DAC63204EVM PCB Layers 17 List of Tables Table 1 1 Contents of DAC63204EVM Kit 3 Table 1 2 Optional Components Not Included With Kit 3 Table 1 3 Related Documentation 3 Table 2 1 DA...

Page 3: ...evaluation board PCB 1 USB micro B plug to USB A plug cable 1 Table 1 2 Optional Components Not Included With Kit Item Quantity BOOSTXL DAC PORT digital to analog converter DAC BoosterPack plug in module 1 TM4C1294 Connected LaunchPad Evaluation Kit EK TM4C1294XL In this document the LaunchPad Evaluation Kit is referred to as TI launchpad 1 These optional components are available for purchase from...

Page 4: ... folders After the software is downloaded navigate to the download folder and run the DAC63204EVM software installer executable When the DAC63204EVM software is launched an installation dialog window opens and prompts the user to select an installation directory If left unchanged the software location defaults to C Program Files x86 Texas Instruments DAC63204EVM as shown in Figure 2 1 Figure 2 1 S...

Page 5: ...ocal machine The FTDI USB drivers install in a second executable shown in Figure 2 2 that is automatically launched after the DAC63204EVM software installation is complete Figure 2 2 FTDI USB Drivers www ti com System Setup SLAU866 NOVEMBER 2021 Submit Document Feedback DAC63204EVM User s Guide 5 Copyright 2021 Texas Instruments Incorporated ...

Page 6: ...crucial to the proper operation of the EVM Table 2 2 provides the details of the configurable jumper settings on the EVM The DAC63204EVM pin numbers are defined in Figure 4 1 Table 2 2 DAC63204EVM Jumper Settings Jumper Default Position Available Option Description J3 Closed 5 V USB supply connected to DAC VDD Open 5 V USB supply disconnected from DAC VDD External or onboard VDD selection J5 2 3 I...

Page 7: ...ed to disconnect the onboard controller GPIO I2C and SPI signals from the DAC signals while the DAC is running in stand alone mode VDD DAC_OUT3 DAC_FB2 DAC_OUT2 DACx3204 DAC_SCLK DAC_SDO DAC_SCL EXT_REF DAC_SDI GND GND GND DAC_SYNC DAC_SDA DAC_GPIO DAC_VREF DAC_CAP DAC_FB0 DAC_OUT0 DAC_OUT1 DAC_FB1 NC FTDI_GPIO3 DAC_VREF GND GND NC NC GND GND GND J2 J1 Controller GPIO Lines I 2 C Lines SPI Lines D...

Page 8: ...back pin for DAC VOUT0 14 DAC_OUT0 Output pin for DAC VOUT0 15 DAC_OUT1 Output pin for DAC VOUT1 16 DAC_FB1 Feedback pin for DAC VOUT1 Table 3 2 DAC63204EVM J2 Pin Definitions Pin Signal Description 1 DAC_VDD VDD power supply for DAC 2 DAC_SCLK SPI SCLK 3 DAC_SDO SPI SDO 4 DAC_SCL I2C SCL 5 EXT_REF External Reference input for DAC 6 GND Ground 7 GND Ground 8 GND Ground 9 NC Not connected 10 NC Not...

Page 9: ...UI Location If the onboard controller is connected correctly the status bar at the bottom of the screen displays CONNECTED as shown in Figure 3 3 If the controller is not properly connected or not connected at all the status displays DEMO If the GUI is not displaying the CONNECTED status while the EVM is connected unplug and reconnect the EVM and then relaunch the GUI software Figure 3 3 DAC63204E...

Page 10: ...ow Level Configuration page Before using the GUI see the respective device data sheet for detailed DACx3204 programming instructions 3 2 2 1 High Level Configuration Page The High Level Configuration page shown in Figure 3 4 provides an interface to quickly configure the parameters and relevant register settings for the respective DACx3204 device The High Level Configuration page consists of the B...

Page 11: ...down mode by default The Basic DAC subpage also provides controls to configure the GPIO pin on the respective DACx3204 device and control the two GPIO outputs of the DAC63204EVM onboard controller The register settings can be programmed or retrieved using the Program NVM or Reload NVM checkboxes respectively Figure 3 5 Basic DAC Subpage www ti com Detailed Description SLAU866 NOVEMBER 2021 Submit ...

Page 12: ...ach DAC channel The Code Step and Slew Rate drop down menu settings are also provided on this page to control the slew of each margin high or low trigger Trigger MHx The register settings can be programmed or retrieved using the Program NVM or Reload NVM checkboxes respectively Figure 3 6 Margining Subpage Detailed Description www ti com 12 DAC63204EVM User s Guide SLAU866 NOVEMBER 2021 Submit Doc...

Page 13: ... saw tooth inverse saw tooth square or sine The Margin High Code and Margin Low Code settings define the upper and lower bounds of the waveform respectively The Start Function Gen checkboxes start or stop the defined function generation for each channel The register settings can be programmed or retrieved using the Program NVM or Reload NVM checkboxes respectively Figure 3 7 Function Generation Su...

Page 14: ...tion The stored configuration files can be recalled and loaded by selecting Open Configuration Figure 3 9 shows the four configuration buttons provided on the Low Level Configuration page that allow the user to read from and write to the device registers Write Selected Write Modified Read Selected Read All The Write Modified button is enabled only in Deferred Update Mode Deferred Update Mode initi...

Page 15: ...ND VCCIO_FTDI DAC_VDD 100nF C15 100nF C13 GND GND Level Translator for SPI DAC_SDI DAC_SYNC DAC_SCLK Level Translator for I2C VCCA 3 VCCB 7 SDA_A 4 SDA_B 1 SCL_A 5 SCL_B 8 OE 6 GND 2 TCA9406DCTR U2 VCCIO_FTDI VCCIO_FTDI DAC_VDD GND Level Shi ers DAC_SCL DAC_SDA Level Shifter Enables Output To DAC USB_VBUS USB_VBUS VCCIN_FTDI USB_VBUS USB_VBUS DAC_SCLK DAC_SDA DAC_SDI DAC_SYNC DAC_SCL DAC_SDO Level...

Page 16: ... EXT_REF DAC_SDI DAC_SYNC DAC_SDA DAC_GPIO 0 R13 0 R15 DAC_GPIO SDO DAC_GPIO DAC_SDO 0 R17 0 R19 DAC_SCL SYNC DAC_SCL DAC_SYNC 0 R14 0 R16 DAC_A0 SDI DAC_A0 DAC_SDI 0 R18 0 R20 DAC_SDA SCLK DAC_SDA DAC_SCLK 10 0k R10 DNP 10 0k R12 DNP GND DAC_VDD DAC_A0 Interface selection I2C SPI 100nF 50V C1 2 2µF 10V C5 10 0k R11 DNP GND 0 R9 EXT_REF DAC_VREF GND DAC configured for Voltage outputs DAC_VREF DAC_...

Page 17: ...4EVM PCB Components Layout Figure 4 4 DAC63204EVM PCB Layers www ti com Schematic PCB Layout and Bill of Materials SLAU866 NOVEMBER 2021 Submit Document Feedback DAC63204EVM User s Guide 17 Copyright 2021 Texas Instruments Incorporated ...

Page 18: ...2x1 Tin TH Header 2 54mm 2x1 TH TSW 102 23 T S Samtec J4 1 Receptacle USB 2 0 Micro USB Type B R A SMT USB micro B USB 2 0 0 65mm 5 Pos R A SMT 10118194 0001LF FCI J5 1 Header 2 54mm 3x1 Gold TH Header 2 54mm 3x1 TH TSW 103 08 G S Samtec L1 1 600 ohm Ferrite Bead 600 ohm 100 MHz 1 A 0603 0603 782633601 Wurth Elektronik R1 R2 R3 R4 R25 5 3 32 k RES 3 32 k 1 0 1 W 0603 0603 RC0603FR 073K32L Yageo Am...

Page 19: ...0FKEA Vishay Dale U1 1 Automotive Smart DACs for Animation and Fault Management With I 2C SPI GPIO and PWM Interface WQFN16 DAC63204RTER Texas Instruments U2 U6 2 Voltage Level Translator Bidirectional 1 Circuit 2 Channel 24Mbps SM8 SSOP8 TCA9406DCTR Texas Instruments U3 1 USB2 0 to QuadSPI I2C Bridge IC VQFN 32 VQFN 32 FT4222HQ D R FTDI U4 1 4 Bit Fixed Direction Voltage Level Translator with Sch...

Page 20: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 21: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 22: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 23: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 24: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 25: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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