Enhanced SPI Module Overview
986
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
C28 Serial Peripheral Interface (SPI)
•
SPICTL (SPI operation control register). Contains control bits for data transmission
–
Two SPI interrupt enable bits
–
SPICLK phase selection
–
Operational mode (master/slave)
–
Data transmission enable
•
SPISTS (SPI status register). Contains two receive buffer status bits and one transmit buffer status bit
–
RECEIVER OVERRUN
–
SPI INT FLAG
–
TX BUF FULL FLAG
•
SPIBRR (SPI baud rate register). Contains seven bits that determine the bit transfer rate
•
SPIRXEMU (SPI receive emulation buffer register). Contains the received data. This register is used
for emulation purposes only. The SPIRXBUF should be used for normal operation
•
SPIRXBUF (SPI receive buffer — the serial receive buffer register). Contains the received data
•
SPITXBUF (SPI transmit buffer — the serial transmit buffer register). Contains the next character to be
transmitted
•
SPIDAT (SPI data register). Contains data to be transmitted by the SPI, acting as the transmit/receive
shift register. Data written to SPIDAT is shifted out on subsequent SPICLK cycles. For every bit shifted
out of the SPI, a bit from the receive bit stream is shifted into the other end of the shift register
•
SPIPRI (SPI priority register). Contains bits that specify interrupt priority and determine SPI operation
on the XDS™ emulator during program suspensions.
12.1.4 SPI Operation
This section describes the operation of the SPI. Included are explanations of the operation modes,
interrupts, data format, clock sources, and initialization. Typical timing diagrams for data transfers are
given.
12.1.4.1 Introduction to Operation
shows typical connections of the SPI for communications between two controllers: a master
and a slave.
The master initiates data transfer by sending the SPICLK signal. For both the slave and the master, data
is shifted out of the shift registers on one edge of the SPICLK and latched into the shift register on the
opposite SPICLK clock edge. If the CLOCK PHASE bit (SPICTL.3) is high, data is transmitted and
received a half-cycle before the SPICLK transition (see
). As a result, both controllers
send and receive data simultaneously. The application software determines whether the data is
meaningful or dummy data. There are three possible methods for data transmission:
•
Master sends data; slave sends dummy data.
•
Master sends data; slave sends data.
•
Master sends dummy data; slave sends data.
The master can initiate data transfer at any time because it controls the SPICLK signal. The software,
however, determines how the master detects when the slave is ready to broadcast data.
