Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
CM3 Core
Instructions
Data
Flash
Patch and
Breakpoint
Memory
Protection
Unit
Debug
Access Port
Nested
Vectored
Interrupt
Controller
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ARM
Cortex-M3
Overview
1606
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
Cortex-M3 Processor
Figure 24-1. Cortex-M3 Processor Block Diagram
24.3 Overview
24.3.1 System-Level Interface
The Cortex-M3 processor provides multiple interfaces using AMBA
®
technology to provide high-speed,
low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit
manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data
handling.
The processor has a memory protection unit (MPU) that provides fine-grain memory control, enabling
applications to implement security privilege levels and separate code, data and stack on a task-by-task
basis.
24.3.2 System Component Details
The Cortex™-M3 processor includes the following system components:
•
SysTick
A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer or as
a simple counter (see System Timer (SysTick) in the
Cortex-M3 Peripherals
chapter).
•
Nested Vectored Interrupt Controller (NVIC)
An embedded interrupt controller that supports low latency interrupt processing (see Nested Vectored
Interrupt Controller (NVIC) in the
Cortex-M3 Peripherals
chapter).
•
System Control Block (SCB)
The programming model interface to the processor. The SCB provides system implementation
information and system control, including configuration, control, and reporting of system exceptions(
see System Control Block (SCB) in the
Cortex-M3 Peripherals
chapter).
•
Memory Protection Unit (MPU)
Improves system reliability by defining the memory attributes for different memory regions. The MPU
