1
0
5-8 data bits
LSB
MSB
Parity bit
if enabled
1-2
stop bits
UnTX
n
Start
Functional Description
1491
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse
has been detected. Overrun, parity, frame error checking, and line-break detection are also performed,
and their status accompanies the data that is written to the receive FIFO.
Figure 21-2. UART Character Frame
21.3.2 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The
number formed by these two values is used by the baud-rate generator to determine the bit period. Having
a fractional baud-rate divider allows the UART to generate all the standard baud rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register and the 6-
bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register. The baud-
rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the
BRD and BRDF is the fractional part, separated by a decimal place).
BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate)
where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE in
UARTCTL is clear) or 8 (if HSE is set).
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can
be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to
account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 8x or 16x the baud-rate (referred to as
Baud8 and Baud16, depending on the setting of the HSE bit (bit 5) in UARTCTL). This reference clock is
divided by 8 or 16 to generate the transmit clock, and is used for error detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register, the UARTIBRD and UARTFBRD
registers form an internal 30-bit register. This internal register is only updated when a write operation to
UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the
UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
•
UARTIBRD write, UARTFBRD write, and UARTLCRH write
•
UARTFBRD write, UARTIBRD write, and UARTLCRH write
•
UARTIBRD write and UARTLCRH write
•
UARTFBRD write and UARTLCRH write
21.3.3 Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four
bits per character for status information. For transmission, data is written into the transmit FIFO. If the
UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the
UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The
BUSY bit in the UART Flag (UARTFR) register is asserted as soon as data is written to the transmit FIFO
(that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is
negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift
register, including the stop bits. The UART can indicate that it is busy even though the UART may no
longer be enabled.
