System Control Registers
188
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
System Control and Interrupts
1.13.3 Reset Control and Status Registers
1.13.3.1 Subsystem Reset Configuration/Control (CRESCNF) Register
Figure 1-48. Subsystem Reset Configuration/Control (CRESCNF) Register
31
18
17
16
Reserved
ACIBRESET
M3RSnIN
R-0:0
R/W-0
R/W-0
15
1
0
Reserved
Reserved
R-0
R-1
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 1-59. Subsystem Reset Configuration/Control (CRESCNF) Register Field Descriptions
Bit
Field
Value
Description
31-18
Reserved
Reserved
17
ACIBRESET
M3 Reset to ACIB
0
ACIBRESET to ACIB is low, causing a ACIB reset (holds Analog Subsystem in reset).
1
ACIBRESET to ACIB is high, enabling ACIB operation (allowing Analog Subsystem to run).
16
M3RSnIN
M3 Reset to C28 CPU
0
RSn to C28 CPU is low, causing a C28 CPU and C28 subsystem reset.
1
RSn to C28 CPU is high, bringing out the C28 CPU and subsystem out of reset.
15-0
Reserved
Reserved
1.13.3.2 Control Subsystem Reset Status (CRESSTS) Register
Figure 1-49. Control Subsystem Reset Status (CRESSTS) Register
31
19
18
17
16
Reserved
CHWBISTRST
CNMIWDRST
R-0
R/W-1
R/W-1
15
1
0
Reserved
CRES
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 1-60. Control Subsystem Reset Status (CRESSTS) Register Field Descriptions
Bit
Field
Value
Description
31-19
Reserved
Reserved
18-17
CHWBISTRST
C28 Reset Cause Flag – set by hardware when C28 HWBIST controller fired a reset to the C28
CPU; this flag does not indicate fail conditions – fail conditions cause an NMI to the M3 and C28
CPUs
00
C28 CPU was not reset due to C28 HW BIST reset
11
C28 CPU was reset due to C28 HW BIST reset
This status bit is a latched flag This flag can be cleared by the M3 CPU by writing a “1”
Note:
This flag is 2 bits to take care of any error conditions that may cause inadvertent setting of a
single bit flag;