CAN Control Registers
1555
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Controller Area Network (CAN)
23.15.14 IF1 and IF2 Command Registers (CAN IF1CMD, CAN IF2CMD)
The IF1 and IF2 Command registers configure and initiate the transfer between the IF1 or IF2 Register
sets and the Message RAM. It is configurable which portions of the message object should be transferred.
A transfer is started when the CPU writes the message number to bits [7:0] of the IF1 or IF2 Command
Register.
With this write operation, the Busy bit is automatically set to '1' to indicate that a transfer is in progress.
After 4 to 14 clock cycles, the transfer between the Interface Register and the Message RAM will be
completed and the Busy bit is cleared. The maximum number of cycles is needed when the message
transfer concurs with a CAN message transmission, acceptance filtering, or message storage.
If the CPU writes to both IF1 and IF2 Command registers consecutively (request of a second transfer
while first transfer is still in progress), the second transfer will start after the first one has been completed.
The following points must be borne in mind while writing to this register: (1) Do not write zeros to the
whole register. (2) Write to the register in a single 32-bit write or write the upper 16-bits before writing to
the lower 16- bits.
NOTE:
While Busy bit is 1, IF1 and IF2 register sets are write protected.
NOTE:
For debug support, the auto clear functionality of the IF1 or IF2 Command Registers is
disabled during Debug mode.
NOTE:
If an invalid Message Number is written to bits [7:0] of the IF1 or IF2 Command Register, the
message handler may access an implemented (valid) message object instead.
Figure 23-32. IF1 Command Registers (CAN IF1CMD) [offset = 0x100]
31
24
23
22
21
20
19
18
17
16
Reserved
WR/R
D
Mask
Arb
Contro
l
Clr
IntPnd
TxRqst
/
NewD
at
Data A Data B
R-0
R/WP-
0
R/WP-
0
R/WP-
0
R/WP-
0
R/WP-
0
R/WP-
0
R/WP-
0
R/WP-
0
15
14
13
8
7
0
Busy
DMA
active
Reserved
Message Number
R-0
R/WP/
C-0
R-0
R/WP-0x1
LEGEND: R = Read; WP = Protected Write (protected by Busy bit); C = Clear by IF1 access; -
n
= value after reset
Figure 23-33. IF2 Command Registers (CAN IF2CMD) [offset = 0x120]
31
24
23
22
21
20
19
18
17
16
Reserved
WR/R
D
Mask
Arb
Contro
l
Clr
IntPnd
TxRqst
/
NewD
at
Data A Data B
R-0
R/WP-0
R/WP-
0
R/WP-
0
R/WP-
0
R/WP-
0
R/WP-
0
R/WP-0
R/WP-0
15
14
13
6
5
0
Busy
DMA
active
Reserved
Message Number
R-0
R/WP/
C-0
R-0
R/WP-0x1
LEGEND: R = Read; WP = Protected Write (protected by Busy bit); C = Clear by IF2 access; -
n
= value after reset
