General Description
2
General Description
The CDCM6208 is a highly-versatile, low-jitter, low-power frequency synthesizer generating up to eight
clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power
CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML,
LVPECL, LVDS, or LVCMOS signals. It also features an innovative fractional divider architecture for four
of its outputs generating any frequency with better than 1 ppm frequency accuracy. The device is easily
configured through I
2
C or SPI programming interfaces. In the absence of serial interface, pin-programming
mode is available and can set the device in many distinct preprogrammed configurations using control
pins. Two versions are available, (CDCM62008V1 and CDCM6208V2) depending on the VCO frequency
ranges.
The CDCM6208 is programmed through an SPI or I
2
C interface using the supplied EVM programming
graphical user interface (GUI).
The CDCM6208 evaluation module (EVM) demonstrates the electrical performance of the device. This
fully-assembled, factory-tested evaluation board allows complete validation of all device functions. For
optimum performance, the board is equipped with 50-
Ω
SMA connectors and well-controlled 50-
Ω
impedance micro strip transmission lines.
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Signal Path and Control
The CDCM6208 provides two selectable inputs – PRI_REF and SEC_REF. The PRI_REF and SEC_REF
accept either differential- (CML, LVDS) or single-ended LVCMOS signals, up to 250 MHz. Besides the
external clocks, SEC_REF allows the use of an external crystal in the frequency range of 10 MHz to 50
MHz. The EVM provides a PC-board footprint for mounting a 3.2 mm × 2.5 mm SMD crystal. If the
SEC_REF is driven through the SMA connector, the on-board crystal and R72 and R73 must be removed
and R87 must be populated with a 0-
Ω
resistor (R89 must also be populated with a 0-
Ω
resistor for a
differential input signal). The device does not have any internal termination or biasing, therefore, proper
biasing and termination options are available on the EVM, if needed.
The CDCM6208 provides up to eight differential signals. Out of eight outputs, four differential outputs can
convert into eight singled LVCMOS signals. A maximum of eight differential or 4 differential and eight
singled LVCMOS clocks or any of the various combinations are possible.
The device operates as a jitter cleaner or as a frequency synthesizer. The CDCM6208 requires a partially-
external loop filter. The EVM provides four loop filter options – two filters are for synthesizer mode and the
other two for jitter-cleaning mode. The loop-filter selection affects the phase noise and loop stability of the
PLL.
In pin mode, the device option is selected by five control pins. In programming mode, options are selected
by programming the on-chip registers. The
data sheet provides the detailed information
needed for configuration and use of this device.
Four outputs (Y0-Y3) are configurable as an LVDS, CML, or LVPECL and another four outputs (Y4-Y7)
are configurable as LVDS, HCSL, or LVCMOS. All outputs are connected to SMA with AC coupling. Y4-Y7
outputs provide the options of 50
Ω
to ground (for HCSL outputs).
The LVCMOS outputs can operate at frequencies up to 200 MHz. The HS-CML and NS-CML outputs
operate at up to 800 MHz. The LP-CML and HCSL outputs operate at up to 400 MHz.
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Software-Selectable Option
The EVM control software communicates with the CDCM6208 through a USB interface and the
CDCM6208 SPI or I
2
C port. The USB controller is normally powered over the USB cable. When the
USB/SPI or USB/I
2
C programming interface is available for use, the on-board LED, D3, is illuminated.
The CDCM6208 GUI can save device configurations into a configuration file (.INI), which are loaded at a
later time restoring the saved settings.
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SCAU049 – May 2012
CDCM6208 Evaluation Board
Copyright © 2012, Texas Instruments Incorporated
