Texas Instruments CDCLVP111EVM-CVAL, User Manual, Page: 5 / 13

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CDCLVP111-SP EVM Description
5 SCAU055 – November 2016
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CDCLVP111-SP Evaluation Module (CDCLVP111EVM-CVAL)
Figure 3. Input Biasing Schematic
Figure 4. Input Biasing Board View
The board also is designed to allow LVDS termination. This is accomplished by the careful layout of R1,
R2, R4 and R5. The pad placements are such that an 0402 100-
Ω resistor can be placed between the top
pads of R1 and R5 or R2 and R4 to differentially terminate either CLK0 or CLK1 pairs respectively (see
Figure 5 ).