CC112X/CC1175
SWRU295C
Page 46 of 108
8 (5
⊕
0)
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
0
0
1
1
1
0
1
1
1
1
0
0
1
1
1
0
1
1
1
1
0
0
1
1
1
0
1
1
1
0
0
0
1
1
1
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
0
0
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
Table 24: PN9 Whitening Sequence
0x80
⊕
0xE1 = 0x61
0xFF
⊕
0x1D = 0xE2
0x00
⊕
0x9A = 0x9A
.
.
.
The complete packet will look like this (assume default preamble, sync word, and CRC configuration):
0xAA, 0xAA, 0xAA, 0xAA, 0x93, 0x0B, 0x51, 0xDE, 0x54, 0x61, 0xE2, 0x9A, 0xF9, 0x9D
7.1.7
Data Byte Swap
If the
register field is set than the bits in each byte are swapped,
meaning that bit 0 becomes bit 7, bit 1 becomes bit 6 etc. until bit 7 becomes bit 0.
In TX mode all bytes in the TX FIFO are swapped before optional CRC calculation and whitening are
performed.
In RX mode the data byte is swapped after all the processing is done, meaning that de-whitening and
CRC calculation are done on the original received data, and the swapping is done right before the
actual writing to the RX FIFO. This means that if using address filtering (see Section 7.2.1) is used