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5 Device Comparison Table
BQ76942 Device Family
PART NUMBER
Communications Interface
CRC Enabled
REG1 LDO Default
BQ76942
I
2
C
N
Disabled
BQ7694201
SPI
Y
Disabled
BQ7694202
I
2
C
Y
Enabled, set to 3.3 V
BQ7694203
SPI
Y
Enabled, set to 5 V
BQ7694204
SPI
Y
Enabled, set to 3.3 V
6 Pin Configuration and Functions
48
VC10
13
VC3
1
NC
36
REGIN
47
BA
T
14
VC2
2
VC9
35
REG1
46
CP1
15
VC1
3
NC
34
REG2
45
CHG
16
VC0
4
VC8
33
RST_SHUT
44
NC
17
VSS
5
NC
32
DDSG
43
DSG
18
SRP
6
VC7
31
DCHG
42
P
ACK
19
NC
7
NC
30
DFETOFF
41
LD
20
SRN
8
VC6
29
CFETOFF
40
PCHG
21
TS1
9
NC
28
HDQ
39
PDSG
22
TS2
10
VC5
27
SDA
38
FUSE
23
TS3
11
NC
26
SCL
37
BREG
24
REG18
12
VC4
25
ALERT
Not to scale
Figure 6-1. Pinout (top)
Table 6-1. BQ76942 TQFP Package (PFB) Pin Functions
PIN
I/O
TYPE
DESCRIPTION
NO.
NAME
1
NC
—
—
This pin is not connected to silicon.
2
VC9
I
IA
Sense voltage input pin for the ninth cell from the bottom of the stack, balance current
input for the ninth cell from the bottom of the stack, and return balance current for the tenth
cell from the bottom of the stack
3
NC
—
—
This pin is not connected to silicon.
SLUSE14B – DECEMBER 2020 – REVISED DECEMBER 2021
4
Copyright © 2021 Texas Instruments Incorporated
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