Texas Instruments bq76925EVM, User Manual

Page: 8 / 44

Circuit Details and Configuration
www.ti.com
Table 3. JTAG Interface Connection
Header Name Terminal Label Purpose
CN7 1 1 TDI/TDO
2 – VCC-TOOL
3 – TDI/VPP
4 – VCC-TARGET
5 – TMS
6 – NONE
7 – TCK
8 – TEST/VPP
9 – GROUND
10 – NONE
11 – RESET
12 – NONE
13 – NONE
14 – NONE
2.1.6 Pack Status (CN5)
The Pack Status header is provided as a convenience for those users desiring to develop firmware for the
MSP430. The default firmware does not use these pins. This connector can be used for GPIO or for an
SPI interface. Total current sourcing from these pins must be limited such that the current rating of the
3.3-V source of the bq76925 circuit is not exceeded. Consult the data sheet for details.
Table 4. Pack Status Connection
Header Name Terminal Label Purpose
CN5 1 GPIO1 GPIO, RXD, SOMI
2 GPIO2 GPIO, TXD
(1)
, SIMO
3 GPIO3 GPIO, SCLK
4 GND Ground
(1)
Silkscreen on the board incorrectly reads RXD
2.2 Configuration Jumpers and Switches (J1 – J6, S2, S4)
Two- and three-terminal headers allow the user to configure the operation of the EVM by installing a shunt
at the header. The description of each jumper header is shown in the following tables. Shunts are
provided with the EVM in the default position.
Table 5. J1, BAT Pin Circuit Configuration
Header Name Position Purpose
1 - 2 Zener diode and series diode in BAT pin circuit
(default)
J1
2 - 3 Only series resistor in BAT pin circuit.
Table 6. J2, VCTL Pin Circuit Configuration
Header Name Position Purpose
1 - 2 Internal V3P3 selected. Not recommended when
SOC LEDs are being used.
J2
2 - 3 External V3P3 selected. (default)
8 bq76925EVM Evaluation Module SLUU514 – July 2011
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated