Texas Instruments BQ25157, Manual

Page: 30 / 110

Table 9-5. Interrupt Triggers and Fault Condition Response (continued)
FAULT / FLAG DESCRIPTION
INTERRUPT
TRIGGER
BASED ON
STATUS BIT
CHANGE
CHARGER
BEHAVIOR
CHARGER
SAFETY TIMER
LS/LDO
BEHAVIOR
PMID
BEHAVIOR
NOTES
TSHUT
No flag. Die
temperature
exceeds thermal
shutdown
threshold is
reached
N/A Disabled Disabled Disabled Disabled
9.3.10 Power Good ( PG) Pin
The PG pin is an open-drain output that by default indicates when a valid IN supply is present. It may also be
configured to be a general purpose output (GPO) controlled through I
2
C or to be a level shifted version of the
MR input signal. Connect PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED
for visual indication. Below is the description for each configuration:
• In its default state, PG pulls to GND when the following conditions are met: V
IN
> V
UVLO
, V
IN
> V
BAT
+V
SLP
and
V
IN
< V
IN_OVP
. PG is high impedance when the input power is not within specified limits.
• MR shifted (MRS) output when the PG_MODE bits are set to 01. PG is high impedance when the MR input is
high, and PG pulls to GND when the MR input is low.
• General purpose open drain output when setting the PG_MODE bits to 1x. The state of the PG pin is then
controlled through the GPO_PG bit, where if GPO_PG is 0 , the PG pin is pulled to GND and if it is 1, the PG
pin is in high impedance.
9.3.11 External NTC Monitoring (TS)
The I
2
C interface allows the user to easily implement the JEITA standard for systems where the battery pack
thermistor is monitored by the host. Additionally, the device provides a flexible voltage based TS input for
monitoring the battery pack NTC thermistor. The NTC thermistor is biased by the device with I
TS_BIAS
and the
resulting voltage at TS is monitored to determine that the battery is at a safe temperature during charging. The
TS pin is not biased continuously, instead it is biased only when the voltage at the pin is being sampled (for
about 25ms in 225ms intervals when VIN is present. Note that the TS biasing cannot be disabled when VIN is
present.
The part can be configured to meet JEITA requirements or a simpler HOT/COLD function only. Additionally, the
TS charger control function can be disabled. To satisfy the JEITA requirements, four temperature thresholds are
monitored: the cold battery threshold, the cool battery threshold, the warm battery threshold, and the hot battery
threshold. These temperatures correspond to the V
COLD
, V
COOL
, V
WARM
, and V
HOT
thresholds in the Electrical
Characteristics table. Charging and safety timers are suspended when V
TS
< V
HOT
or V
TS
> V
COLD
. When V
COOL
< V
TS
< V
COLD
, the charging current is reduced to the value programmed in the TS_FASTCHGCTRL register.
Note that the current steps for fast charge in the COOL region, just as those in normal fast charge, are multiples
of the fast charge LSB value (1.25 mA by default). So in the case where the calculated scaled down current for
the COOL region falls in between charge current steps, the device will round down the charge current to the
nearest step. For example, if the fast charge current is set for 15 mA (ICHG = 1100) and TS_FASTCHARGE
=111 (0.125*ICHG), the charge current in the COOL region will be 1.25 mA instead of the calculated 1.85 mA.
When V
HOT
< V
TS
< V
WARM
, the battery regulation voltage is reduced to the value programmed in the
TS_FASTCHGCTRL register.
Regardless of whether the part is configured for JEITA, HOT/COLD, or disabled, when a TS fault occurs, a 128-
µs pulse is sent on the INT output, and the FAULT bits of the register are updated over I
2
C. The FAULT bits are
not cleared until they are read over I
2
C. This allows the host processor to take action if a different behavior than
the pre-set function is needed. Alternately, the TS pin voltage can be read by the host if VIN is present or when
BAT is present, so the appropriate action can be taken by the host.
BQ25157
SLUSEC5 – DECEMBER 2020
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