To avoid I
2
C hang-ups, a timer (t
I2CRESET
) runs during I
2
C transactions. If the SDA line is held low longer than
t
I2CRESET
, any additional commands are ignored and the I
2
C engine is reset. The timeout is reset with START
and repeated START conditions and stops when a valid STOP condition is sent.
9.5.2 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in
. All I
2
C-compatible devices should
recognize a start condition.
START Condition
DATA
CLK
STOP Condition
S
P
Figure 9-7. Start Stop Condition
The master then generates the SCL pulses, and transmits the address and the read/write direction bit R/W on
the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the
SDA line to be stable during the entire high period of the clock pulse (see
). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates and acknowledge (see
) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting the acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 9-8. Bit Transfer on the Serial Interface
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
Not Acknowledge
Acknowledge
Clock Pulse for
Acknowledgement
1
2
8
9
START
Condition
Figure 9-9. Acknowledge on the I
2
C Bus
SLUSDI4A – OCTOBER 2018 – REVISED APRIL 2021
Copyright © 2022 Texas Instruments Incorporated
33
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