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12 Layout

12.1 Layout Guidelines

• Keep the core components of the system close to each other and the device.
• Keep the PMID, IN, and SYS caps as close to their respective pins as possible. Place the bypass caps for

PMID, SYS, and LSLDO close to the pins.

• Place the GNDs of the PMID and IN caps close to each other.
• Don’t route so the power planes are interrupted.

12.2 Layout Example

Figure 12-1. BQ25121A Layout

BQ25121A

SLUSDA7A – APRIL 2018 – REVISED JANUARY 2021

www.ti.com

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BQ25121A

Summary of Contents for BQ25120A

Page 1: ...ty Related Certification TUV IEC 62368 1 Certification 2 Applications Smart Watches and other Wearable Devices Fitness Accessories Health Monitoring Medical Accessories Rechargeable Toys 3 Description...

Page 2: ...umentation Support 65 13 1 Device Support 65 13 2 Receiving Notification of Documentation Updates 65 13 3 Trademarks 65 13 4 Support Resources 65 13 5 Electrostatic Discharge Caution 65 13 6 Glossary...

Page 3: ...infrequently used devices The manual reset with timer allows multiple different configuration options for wake are reset optimization A simple voltage based monitor provides battery level information...

Page 4: ...only is present and disable charge when VIN is present CD is pulled low internally with 900 k SDA E4 I O I2C Interface Data Connect SDA to the logic rail through a 10 k resistor SCL E5 I I2C Interfac...

Page 5: ...00k resistor RESET D3 O Reset Output RESET is an open drain active low output that goes low when MR is held low for longer than tRESET which is configurable by the MRRESET registers RESET is deasserte...

Page 6: ...discharge Human body model HBM per ANSI ESDA JEDEC JS 001 1 2000 V Charged device model CDM per JEDEC specification JESD22 C101 2 500 1 JEDEC document JEP155 states that 500 V HBM allows safe manufac...

Page 7: ...ction to board thermal resistance 12 0 C W JT Junction to top characterization parameter 1 2 C W JB Junction to board characterization parameter 12 0 C W R JC bot Junction to case bottom thermal resis...

Page 8: ...ATH MANAGEMENT and INPUT CURRENT LIMIT VDO IN PMID VIN V PMID VIN 5 V IIN 300 mA 125 170 mV VDO BAT PMID V BAT V PMID VIN 0 V V BAT 3 V Iff 400 mA 120 160 mV V BSUP1 Enter supplement mode threshold V...

Page 9: ...UT RDS ON_HS PMID 3 6 V I SYS 675 850 m RDS ON_LS PMID 3 6 V I SYS 300 475 m RDS CH_SYS MOSFET on resistance for SYS discharge VIN 3 6 V IOUT 10 mA into VOUT pin 22 40 I LIMF SW Current limit HS 2 2 V...

Page 10: ...alling 1 VIN Hysteresis 20 1 20 5 20 8 VIN VCOOL Cool temperature threshold VTS rising 1 VIN Hysteresis 35 4 36 36 4 VIN VCOLD Low temperature threshold VTS rising 1 VIN Hysteresis 39 3 39 8 40 2 VIN...

Page 11: ...nk current VPULLUP 1 1 V 0 275 V IBIAS High Level leakage current VPULLUP 1 8 V SDA and SCL 1 A INT PG and RESET OUTPUT Open Drain VOL Low level output threshold Sinking current 5 mA 0 25 x V SYS V II...

Page 12: ...UVLO 350 s tSOFTSTART Softstart time with reduced current limit 400 1200 s LS LDO OUTPUT tON_LDO Turn ON time 100 mA load 500 s tOFF_LDO Turn OFF time 100 mA load 5 s PUSHBUTTON TIMER tWAKE1 Push butt...

Page 13: ...IQ Typical Start Up Timing and Operation VBAT VBUVLO Remove Battery Shows Charge Status VISET 3uA max 4uA max No SYS Load SYS Load Applied 3uA max 5uA max 4uA max nA of leakage with VIN present 0mA Co...

Page 14: ...led up to SYS ISYS 10 A EN_INT 1 Figure 8 2 Battery Operation and Sleep Mode BQ25121A SLUSDA7A APRIL 2018 REVISED JANUARY 2021 www ti com 14 Submit Document Feedback Copyright 2021 Texas Instruments I...

Page 15: ...re qC R DS ON m 40 25 10 5 20 35 50 65 80 95 110 125 0 100 200 300 400 500 600 700 D024 Figure 8 6 Blocking FET RDS ON vs Temperature Temperature qC R DS ON m 40 25 10 5 20 35 50 65 80 95 110 125 0 50...

Page 16: ...Pre Charge Current Temperature qC R DS ON m 40 25 10 5 20 35 50 65 80 95 110 125 0 100 200 300 400 500 600 700 800 900 1000 D026 D024 VIN 5 V Figure 8 12 RDS ON of High Side MOSFET vs Temperature Tem...

Page 17: ...OL SYS 1C 0 5C Disable Disable VBATREG 140mV LDO Load Switch Control IINLIM Q1 Q2 Q3 Q4 VIN_DPM VSUPPLY VBATREG LDO Control VSYSREG Thermal Shutdown Termination Reference IBAT VIN VINOVP VBAT VBATOVP...

Page 18: ...ent the device will enter Ship Mode upon removal of the supply The EN_SHIPMODE bit can be cleared using the I2C interface as well while the IN input is valid In addition to VIN VUVLO CD and MR must be...

Page 19: ...harge Disabled 9 3 3 Active Battery Only Connected When the battery above VBATUVLO is connected with no input source the battery discharge FET is turned on After the battery rises above VBATUVLO and t...

Page 20: ...98 VBMON 94 or 96 VBMON 90 or 92 VBMON 86 or 88 VBMON 84 D E C O D E R S3 S2 S1 S0 2 BAT TAP 4 BAT TAP 6 BAT TAP 8 BAT TAP 10 BAT TAP VREF 90 VB 80 VB 70 VB 60 VB VB 0 8 VBAT VBGUAGE_TH 2 0 Figure 9 3...

Page 21: ...in the control register determines whether a charge cycle is initiated When the CE bit is 1 and a valid input source is connected the battery discharge FET is turned off and the output at SYS is regu...

Page 22: ...an external resistor or through registers over I2C Set the termination current using the IPRETERM pin by connecting a resistor from IPRETERM to GND The termination can be set between 5 and 20 of the...

Page 23: ...ernally programmed value the voltage at ISET reflects the actual charging current and can be used to monitor charge current The current out of ISET is 1 100 10 of the charge current The charge current...

Page 24: ...warm battery threshold and the hot battery threshold These temperatures correspond to the V COLD V COOL V WARM and V HOT threshold in Section 8 5 Charging and timers are suspended when V TS V HOT or...

Page 25: ...The cool and warm NTC resistances for a selected resistor divider are calculated using Equation 3 and Equation 4 COOL COOL COOL LO HI COOL LO LO HI R x R x V R R R x V R x V 3 LO HI WARM WARM LO LO H...

Page 26: ...he PG pin can be configured as a MR shifted MRS output when the PGB_MRS bit is set to 1 PG is high impedance when the MR input is not low and PG pulls to GND when the MR input is below VOL TH_MRS Conn...

Page 27: ...current the PWM to PFM transition point where the part enters and exits Pulse Frequency Modulation to lower the power consumed at low loads the output voltage ripple and the efficiency The selected in...

Page 28: ...Output and Control The device integrates a low Iq load switch which can also be used as a regulated output The LSCTRL pin can be used to turn the load on or off Activating LSCTRL continuously holds th...

Page 29: ...fy the host and the WAKE1 and or WAKE2 bits are updated on I2C The MR_WAKE bits and RESET FAULT bits are not cleared until the Push button Control Register is read from I2C When a MR reset condition i...

Page 30: ...Fault and Status Condition Responses FAULT or STATUS ACTIONS CHARGER BEHAVIOR SYS BEHAVIOR LS LDO BEHAVIOR TS BEHAVIOR VIN_OV Update VIN_OV status Update STAT to fault interrupt on INT PG shown not go...

Page 31: ...ess disabled in OTP or register settings FAULT A failure occurred The fault event must be cleared before going to the previous state DONE The termination requirements have been met VBAT is monitored a...

Page 32: ...atible interface to program and read many parameters I2C is a 2 wire serial interface developed by NXP The bus consists of a data line SDA and a clock line SCL with pull up structures When the bus is...

Page 33: ...er ensures that data is valid A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse see Figure 9 8 All devices recognize the address sent by the ma...

Page 34: ...essed slave All I2C compatible devices must recognize the STOP condition Upon the receipt of a STOP condition all devices know that the bus is released and wait for a START condition followed by a mat...

Page 35: ...us only B6 STAT_0 R x B5 EN_SHIPMODE Write Only 0 0 Normal Operation 1 Ship Mode Enabled B4 RESET_FAULT R x 1 RESET fault Indicates when the device meets the RESET conditions and is cleared after I2C...

Page 36: ...ws only one time Once read VIN_UV clears until another UVLO event occurs B5 BAT_UVLO R x 1 BAT_UVLO fault BAT_UVLO continues to show fault after an I2C read as long as BAT_UVLO conditions exist B4 BAT...

Page 37: ...x Reserved B3 EN_INT R W 1 0 Disable INT function INT only shows faults and does not show charge status 1 Enable INT function INT shows faults and charge status B2 WAKE_M R W 0 1 Mask interrupt from W...

Page 38: ...e mode ICHRG_RANGE and ICHRG bits are used to set the charge current The ICHRG is calculated using the following equation If ICHRG_RANGE is 0 then ICHRG 5 mA ICHRGCODE x 1 mA If ICHRG_RANGE is 1 then...

Page 39: ...PRETERM_RANGE is 0 then ITERM 500 A ITERMCODE x 500 A If IPRETERM_RANGE is 1 then ITERM 6 mA ITERMCODE x 1 mA If a value greater than 5 mA IPRETERM_RANGE 0 is written the setting goes to 5 mA Terminat...

Page 40: ...REG is calculated using the following equation VBATREG 3 6 V VBREGCODE x 10 mV The charge voltage range is from 3 6 V to 4 65 V If a value greater than 4 65 V is written the setting goes to 4 65 V BQ2...

Page 41: ...step if SYS_SEL is 01 or 11 B1 SYS_VOUT_0 R W 0 OUT Voltage 100 mV step if SYS_SEL is 01 or 11 B0 LSB 0 SW_VOUT Bits Use SYS_SEL and SYS_VOUT bits to set the output on SYS The SYS voltage is calculat...

Page 42: ...2 V 10 0111 2 083 V 10 1000 2 167 V 10 1001 2 25 V 10 1010 2 333 V 10 1011 2 417 V 10 1100 2 5 V 10 1101 2 583 V 10 1110 2 667 V 10 1111 2 75 V 11 0000 1 8 V 11 0001 1 9 V 11 0010 2 V 11 0011 2 1 V 11...

Page 43: ...LS_LDO_1 R W 1 LS LDO Voltage 200 mV B2 LS_LDO_0 R W 1 LS LDO Voltage 100 mV B1 0 B0 LSB MRRESET_VIN R W x 0 Reset sent when MR Reset time is met 1 Reset sent when MR Reset time is met and VUVLO VSLP...

Page 44: ...W 1 0 After Reset device enters Ship mode 1 After Reset device enters Hi Z Mode B4 MRRESET_1 R W 0 MR Timer adjustment for reset 00 5 s 20 01 9 s 20 10 11 s 20 11 15 s 20 B3 MRRESET_0 R W 1 B2 PGB_MR...

Page 45: ...the following equation I INLIM 50 mA I INLIM CODE x 50 mA The default may be overridden by the external resistor on ILIM 9 6 11 Voltage Based Battery Monitor Register Memory location 0x0Ah Reset Stat...

Page 46: ...then it will move to VBMON_RANGE 10 80 to 90 and continue until a non 000 value of VBMON_TH is found If this does not happen then VBMON_RANGE and VBMON_TH will be written with 00 000 The VBMON_READ b...

Page 47: ...mV B5 VINDPM_1 R W 0 Input V IN_DPM voltage 200 mV B4 VINDPM_0 R W 0 Input V IN_DPM voltage 100 mV B3 2XTMR_EN R W 0 0 Timer is not slowed at any time 1 Timer is slowed by 2x when in any control othe...

Page 48: ...shows the TS resistors which is also optional When powering up in default mode the battery voltage is the default for the part 4 2 V the SYS output is the default 2 5 V External resistors set the char...

Page 49: ...Design Procedure See Figure 10 1 for an example of the application diagram 10 2 2 1 Default Settings Connect ISET ILIM and IPRETERM pins to ground to program fast charge current to 10 mA input current...

Page 50: ...Resistors TS The voltage at TS is monitored to determine that the battery is at a safe temperature during charging This device uses JEITA temperature profile which has four temperature thresholds Ref...

Page 51: ...500 mV div Figure 10 4 Entering DPPM Mode Time 4 ms div 10 mA div 100 mA div 2 V div 500 mV div Figure 10 5 Exiting DPPM Mode Time 4 ms div 20 mA div 100 mA div 2 V div 500 mV div Figure 10 6 Entering...

Page 52: ...Charger On Off Using CD Time 4 ms div 10 mA div 20 mA div 2 V div 500 mV div Figure 10 9 OVP Fault BQ25121A SLUSDA7A APRIL 2018 REVISED JANUARY 2021 www ti com 52 Submit Document Feedback Copyright 2...

Page 53: ...igure 10 12 1 8 VSYS System Efficiency Load Current A Efficiency 1E 6 1E 5 0 0001 0 001 0 01 0 10 2 0 5 40 50 60 70 80 90 100 D010 3 0 V BAT 3 6 V BAT 3 8 V BAT 4 2 V BAT TA 25 C VSYS 2 5 V Figure 10...

Page 54: ...4 2 V BAT TA 25 C VSYS 2 5 V Figure 10 18 2 5 VSYS Load Regulation Load Current A SYS Output Voltage V 1E 6 1E 5 0 0001 0 001 0 01 0 1 0 5 3 1845 3 2345 3 2845 3 3345 3 3845 D015 3 8 V BAT 4 2 V BAT T...

Page 55: ...PA 10 PA 100 PA 1 mA 10 mA 100 mA 4 2 TA 25 C VSYS 3 3 V Figure 10 24 3 3 VSYS Line Regulation Load Current mA Frequency F SW kHz 0 50 100 150 200 250 300 0 200 400 600 800 1000 1200 1400 D023 5 V VB...

Page 56: ...on Showing SW Time 400 ns div 500 mA div 200 mA div 2 V div 5 V div SW ILOAD 200 mA Figure 10 31 Light Load Operation Showing SW Time 400 ns div 500 mA div 200 mA div 2 V div 5 V div SW ILOAD 300 mA F...

Page 57: ...ient 0 to 50 mA Time 4 s div m 500 mA div 50 mV div 50 mV div 5 V div SW VSYS 3 3 V Figure 10 37 3 3 VSYS Load Transient 0 to 50 mA Time 4 s div m 500 mA div 200 mV div 50 mV div 5 V div SW VSYS 1 2 V...

Page 58: ...0 mA div 200 mV div 50 mV div 5 V div SW VSYS 3 3 V Figure 10 42 3 3 VSYS Load Transient 0 to 200 mA Time 1 ms div 1 V div 5 V div 2 V div Figure 10 43 Startup Showing SS on SYS in PWM Mode Time 20 ms...

Page 59: ...ransient 0 to 10 mA Time 4 s div m 50 mV div 5 V div 20 mV div VSLSDO 1 2 V Figure 10 48 1 2 VLSLDO Load Transient 0 to 10 mA Time 4 s div m 50 mV div 5 V div 20 mV div VSLSDO 1 8 V Figure 10 49 1 8 V...

Page 60: ...ient 0 to 100 mA Time 4 s div m 50 mV div 5 V div 100 mV div VSLSDO 1 8 V Figure 10 54 1 8 VLSLDO Load Transient 0 to 100 mA Time 4 s div m 50 mV div 5 V div 100 mV div VSLSDO 2 5 V Figure 10 55 2 5 V...

Page 61: ...up Showing SS on LS LDO in LDO Mode Time 20 ms div 200 mA div 2 V div 2 V div Figure 10 58 Short Circuit and Recovery for LDO www ti com BQ25121A SLUSDA7A APRIL 2018 REVISED JANUARY 2021 Copyright 202...

Page 62: ...G Functions as Shifted MR Output Time 400 s div m 500 mV div 2 V div 2 V div 5 V div Figure 10 62 PG Functions as Shifted MR Output Time 200 ms div 2 V div 2 V div 500 mV div 2 V div Wake1 500 ms Wake...

Page 63: ...e 10 67 RESET Timing Time 2 s div 2 V div 2 V div 500 mV div 2 V div Figure 10 68 RESET Timing and Enter Ship Mode 11 Power Supply Recommendations It is recommended to use a power supply that is capab...

Page 64: ...Place the bypass caps for PMID SYS and LSLDO close to the pins Place the GNDs of the PMID and IN caps close to each other Don t route so the power planes are interrupted 12 2 Layout Example Figure 12...

Page 65: ...design help you need Linked content is provided AS IS by the respective contributors They do not constitute TI specifications and do not necessarily reflect TI s views see TI s Terms of Use 13 5 Elect...

Page 66: ...0ppm threshold Antimony trioxide based flame retardants must also meet the 1000ppm threshold requirement 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard...

Page 67: ...PACKAGE OPTION ADDENDUM www ti com 10 Dec 2020 Addendum Page 2...

Page 68: ...ns SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant BQ25121AYFPR DSBGA YFP 25 3000 180 0 8 4 2 65 2 65 0 69 4 0 8 0 Q1 BQ25121AYFPT DSBGA YFP 25 250 180 0 8 4 2 65 2 65...

Page 69: ...Package Type Package Drawing Pins SPQ Length mm Width mm Height mm BQ25121AYFPR DSBGA YFP 25 3000 182 0 182 0 20 0 BQ25121AYFPT DSBGA YFP 25 250 182 0 182 0 20 0 PACKAGE MATERIALS INFORMATION www ti c...

Page 70: ...BALL GRID ARRAY NOTES 1 All linear dimensions are in millimeters Any dimensions in parenthesis are for reference only Dimensioning and tolerancing per ASME Y14 5M 2 This drawing is subject to change...

Page 71: ...nal dimensions may vary due to manufacturing tolerance considerations and also routing constraints See Texas Instruments Literature No SNVA009 www ti com lit snva009 SOLDER MASK DETAILS NOT TO SCALE S...

Page 72: ...9 2019 DSBGA 0 5 mm max height YFP0025 DIE SIZE BALL GRID ARRAY NOTES continued 4 Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release SYMM SYMM SOLDER PAS...

Page 73: ...are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and...

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