Texas Instruments Boomer LM49360, User Manual

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TABLE 62. CLK_GEN_1 (0x52h/62h)
Bits Field Description
2:0 SYNTH_NUM Along with SYNTH_DENOM, this sets the clock divider that generates the Port 1 or Port 2 clock in
master mode.
SYNTH_NUM Numerator
000 SYNTH_DENOM (1/1)
001 100/SYNTH_DENOM
010 96/SYNTH_DENOM
011 80/SYNTH_DENOM
100 72/SYNTH_DENOM
101 64/SYNTH_DENOM
110 48/SYNTH_DENOM
111 0/SYNTH_DENOM
3 SYNTH_DENOM Along with SYNTH_NUM, this sets the clock divider that generates the Port 1 or Port 2 clock in master
mode.
SYNTH_DENOM Denominator
0 128
1 125
TABLE 63. CLK_GEN_1 (0x53h/63h)
Bits Field Description
2:0 SYNC_RATE This sets the number of clock cycles before the sync pattern repeats. This depends if the audio port
data is mono or stereo.
In MONO mode:
SYNC_RATE Number of Clock Cycles
000 8
001 12
010 16
011 18
100 20
101 24
110 25
111 32
In STEREO mode:
SYNC_RATE Number of Clock Cycles
000 16
001 24
010 32
011 36
100 40
101 48
110 50
111 64
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