Texas Instruments Boomer LM49360 User Manual Download Page 85

Page: 85 / 137

This register is used to control the LM49360's digital mixer.

TABLE 54. Input Levels 1 (0x40h)

Bits

Field

Description

1:0

PORT1_RX_L

_LVL

This programs the input level of the data arriving from the left receive channel of Audio Port 1.

PORT1_RX_L_LVL

Level

0dB

–6dB

–12dB

–18dB

3:2

PORT1_RX_R

_LVL

This programs the input level of the data arriving from the right receive channel of Audio Port 1.

PORT1_RX_R_LVL

Level

0dB

–6dB

–12dB

–18dB

5:4

PORT2_RX_L

_LVL

This programs the input level of the data arriving from the left receive channel of Audio Port 2.

PORT2_RX_L_LVL

Level

0dB

–6dB

–12dB

–18dB

7:6

PORT2_RX_R

_LVL

This programs the input level of the data arriving from the right receive channel of Audio Port 2.

PORT2_RX_R_LVL

Level

0dB

–6dB

–12dB

–18dB

TABLE 55. Input Levels 2 (0x41h)

Bits

Field

Description

1:0

ADC_L_LVL

This programs the input level of the data arriving from the left ADC channel.

ADC_L_LVL

Level

0dB

–6dB

–12dB

–18dB

3:2

ADC_R_LVL

This programs the input level of the data arriving from the right ADC channel.

ADC_R_LVL

Level

0dB

–6dB

–12dB

–18dB

5:4

INTERP_L_LVL

This programs the input level of the data arriving from the left DAC's interpolator output.

INTERP_L_LVL

Level

0dB

–6dB

–12dB

–18dB

www.ti.com

LM49360

Summary of Contents for Boomer LM49360

Page 1: ...LM49360 LM49360 Mono Class D Audio Codec PMU with Ground Referenced Headphone Amplifiers Earpiece Driver Audio DSP 2 Step Down DC DC Converters and 7 LDO Regulators Literature Number SNAS501A...

Page 2: ...PLS at LS_VDD 3 6V 8 1 THD 595mW typ SNR Stereo DAC at 48kHz 97dB typ PSRR at 217 Hz A_VDD 3 6V HP from AUX 95dB typ 4 0 Features Ultra efficient spread spectrum Class D loudspeaker amplifier Low volt...

Page 3: ...5 0 LM49360 Overview 301282h8 FIGURE 1 LM49360 Block Diagram www ti com 2 LM49360...

Page 4: ...6 0 Typical Application 30128211 FIGURE 2 Sub PMU System Diagram 3 www ti com LM49360...

Page 5: ...30128216 FIGURE 3 AP PMU System Diagram www ti com 4 LM49360...

Page 6: ...1 2 t0 TCC Core Buck2 700 1 8 I2C VT CAM I O LDO1 400 1 8 t4 t0 256 TCC 1 8 I O LDO2 200 2 6 I2C MIC BIAS LDO3 400 2 8 t4 t0 256 TCC 2 8 I O LDO4 200 3 3 I2C DC MOTOR LDO5 200 3 3 t4 t0 256 USB LDO6...

Page 7: ...O 7 21 19 0 Electrical Characteristics Audio CODEC A_VDD LS_VDD 3 6V HP_VDD D_VDD I O_VDD 1 8V 22 20 0 Timing Characteristics DVDD I OVDD 1 8V 27 21 0 Typical Performance Characteristics 29 22 0 Syste...

Page 8: ...RE 30 ADC DSP Effects Chain 94 FIGURE 31 DAC DSP Effects Chain 94 FIGURE 32 ALC Example 96 FIGURE 33 ALC Limiter 97 FIGURE 34 Audio Compressor Effect 105 FIGURE 35 Soft Knee Example with Compression R...

Page 9: ...VEL 0x19h 77 TABLE 48 HP_SENSE 0x1Bh 79 TABLE 49 ADC Basic 0x20h 80 TABLE 50 ADC_CLK_DIV 0x21h 80 TABLE 51 ADC_MIXER 0x23h 81 TABLE 52 DAC Basic 0x30h 82 TABLE 53 DAC_CLK_DIV 0x31h 82 TABLE 54 Input L...

Page 10: ...Bh 117 TABLE 94 EQ_BAND_2 0xACh 118 TABLE 95 EQ_BAND_3 0xADh 119 TABLE 96 EQ_BAND_4 0xAEh 120 TABLE 97 EQ_BAND_5 0xAFh 121 TABLE 98 SOFTCLIP1 0xB0h 122 TABLE 99 SOFTCLIP2 0xB1h 123 TABLE 100 SOFTCLIP3...

Page 11: ...30128250 Order Number LM49360RL See NS Package Number RLA64JBA 64 Bump micro SMD Marking 301282q7 Top View XY Date Code TT Die Traceability G Boomer N6 LM49360RL LM49360RL Pinout Diagram 30128251 Top...

Page 12: ...ckage DWG Transport Media MSL Level Green Status LM49360RL 64 Bump micro SMDxt RLA64JBA 250 units on tape and reel 1 RoHS and no Sb Br LM49360RLX 64 Bump micro SMDxt RLA64JBA 1000 units on tape and re...

Page 13: ...ly Input CONFIG Low In AP PMU mode PWR_ON low enables standby mode and PWR_ON high turns on the BUCK and LDO outputs The PWR_ON pin expects to be driven by Vbatt via an external switch CONFIG High or...

Page 14: ...t G4 MIC Analog Input Microphone negative input G5 PORT1_SDI Digital Input Audio Port 1 serial data input G6 D_VDD Supply Input DAC Digital ADC Digital PLL Digital digital mixer DSP core and I2C regis...

Page 15: ...the opposite order from power up The time between stages is programmable 8 s 64 s 128 s and 256 s The timing for each output can be set individually and can be different for each of the 3 modes The ou...

Page 16: ...301282h9 FIGURE 4 PMU State Machine 15 www ti com LM49360...

Page 17: ...w power os cillator is reused by many circuits in the device that require delays the PMC controls when it should be enabled If the PMC is not using the oscillator i e PMC_CLK_SEL is set to MCLK it wil...

Page 18: ...lick and pop free operation The comparator is then pow ered down If no zero crossing occurs after 11ms assume audio content at frequencies above 36Hz the changes are applied regardless and the control...

Page 19: ...nsumption Unless otherwise noted PVDD VIN1 VIN2 VIN3 VINB1 VINB2 3 6V CVINB1 CVINB2 4 7 F CVIN1 CVIN2 CVIN3 10 F A_VDD LS_VDD 3 6V HP_VDD D_VDD IO_VDD 1 8V Typical values and limits appearing in boldf...

Page 20: ...in voltage is continuously monitored to determine if it is above the UVLO threshold If the PVDD drops below the UVLO threshold an UVLO_EVENT occurs and the PMU state machine returns to the STANDBY sta...

Page 21: ...0 m IOUT 200mA RDSON N Pin Pin resistance for NMOS VIN VGS 3 6V 100 120 m IOUT 200mA ILIM Switch Peak Current Limit Open loop programmable 1020 1200 1360 mA tSTARTUP Start Up Time IOUT 0mA to 100mA 50...

Page 22: ...arameter Condition Min Typ Max Units VOUT Output Voltage Accuracy IOUT 1mA VOUT 1 2V 2 2 IOUT 1mA VOUT 1 2V over temperature 3 3 IOUT Max Output Current VOUT 0 5V VIN3 5 5V 20 40 mA ISC Output Current...

Page 23: ...0 8 mA max AISD Analog Shutdown Current Shutdown Mode 0 1 9 A max AIDD Analog Supply Current MP3 Mode fMCLK 11 2896MHz fS 44 1kHz Stereo DAC On OSRDAC 64 PLL Off Stereo HP On From A_VDD 4 6 6 mA max...

Page 24: ...Hz Mono Input Terminated VREF 1 0 F Input Referred LS Gain 12dB 82 65 dB min VRIPPLE 200mVP P fRIPPLE 217Hz From DAC DAC gain 0dB 80 dB SNR Signal to Noise Ratio Reference VOUT 1 THD N Mono gain 0dB A...

Page 25: ...in Matching 0 03 dB VOS Output Offset Voltage Note 13 AUX Gain 0dB From mono Input 0 25 1 mV max DAC Gain 0dB From DAC Input fMCLK 12 288MHz 0 25 1 mV max AUXILIARY OUTPUT EARPIECE AMPLIFIER THD N Tot...

Page 26: ...DAC Signal to Noise Ratio fS 48kHz A weighted AUXOUT 96 dB VOLUME CONTROL VCRAUX Stereo Input Volume Control Range Minimum Gain 46 5 dB Maximum Gain 18 dB VCRMONO MONO Input Volume Control Range Mini...

Page 27: ...temperatures and is dictated by TJMAX JA and the ambient temperature TA The maximum allowable power dissipation is PDMAX TJMAX TA JA or the number given in Absolute Maximum Ratings whichever is lower...

Page 28: ...aster 20 ns I2S SLAVE TIMING I2S_CLKPER I2S_CLK Period I2S Slave 81 38 ns min tCLK_L I2S_CLK Low Time I2S Slave 37 ns min tCLK_H I2S_CLK High Time I2S Slave 37 ns min tSDO_DLY SDO Propagation Delay fr...

Page 29: ...Symbol Parameter Conditions LM49360 Units Limit Typical Note 6 Limit Note 7 10 Bus Free Time Between a STOP and START Condition 1 3 s min CB Bus Capacitance 200 pF max www ti com 28 LM49360...

Page 30: ...2V Blue LSVDD 5V 0 400 800 1200 1600 2000 0 10 20 30 40 50 60 70 80 90 100 EFFICIENCY OUTPUT POWER mW 301282b2 DAC Frequency Response fS 48kHz Blue OSR 64 Light Blue OSR 128 301282b3 DAC Frequency Res...

Page 31: ...Response fS 48kHz OSR 64 From MIC MIC Gain 6dB CIN 1 F 301282b9 Stereo Audio ADC Frequency Response fS 8kHz OSR 128 From MIC MIC Gain 6dB CIN 1 F 301282c0 Mono Voice ADC Frequency Response fS 48kHz O...

Page 32: ...IN 1 F Gray No HPF Yellow HPF Mode 000 Light Green HPF Mode 001 Green HPF Mode 010 Light Blue HPF Mode 011 Blue HPF Mode 100 301282a5 Mono Voice HPF ADC Frequency Response fS 8kHz OSR 128 From MIC MIC...

Page 33: ...s Frequency From MONO AUX Input MONO AUX Gain 0dB LS Gain 8dB POUT 400mW RL 8 Blue LSVDD 3 6V Light Blue LSVDD 4 2V Green LSVDD 5V 301282h0 Loudspeaker THD N vs Frequency From MONO AUX Input MONO AUX...

Page 34: ...128 MONO AUX Input MONO AUX Gain 0dB LS Gain 12dB LSVDD 4 2V VRIPPLE 200mVPP Input Referred 30128275 Loudspeaker PSRR vs Frequency MONO AUX Input MONO AUX Gain 0dB LS Gain 12dB LSVDD 5V VRIPPLE 200mV...

Page 35: ...0dB HPVDD 2 8V POUT 15mW RL 16 Stereo in Phase 30128264 Headphone PSRR vs Frequency MONO AUX Input MONO AUX Gain 0dB HP Gain 0dB HPVDD 1 8V AVDD 3 6V VRIPPLE 200mVPP Ripple on HPVDD AVDD 30128268 Hea...

Page 36: ...MONO AUX Gain 0dB EP Gain 6dB AVDD 3 6V VRIPPLE 200mVPP Earpiece Mode 301282e6 Auxiliary Output THD N vs Frequency MONO AUX Input MONO AUX Gain 0dB EP Gain 0dB AVDD 3 6V VOUT 1VRMS RL 5k AUXOUT Mode 3...

Page 37: ...82g1 LDO Load Transient VIN 3 6V VOUT 2 0V 1 400mA Load COUT 10 F LDO1 LDO3 301282g2 LDO Load Transient VIN 3 6V VOUT 2 0V 1 200mA Load COUT 1 F LDO2 LDO4 LDO5 LDO6 301282g3 LDO Load Transient VIN 3 6...

Page 38: ...et Timing VIN 3 6V 301282g6 LDO Turn On Time VIN 3 6V Config VBATT 301282g7 LDO Output Ripple VIN 3 6V Buck 1 and 2 On 301282g8 LDO Output Ripple VIN 3 6V Buck 1 and 2 Off 301282g9 37 www ti com LM493...

Page 39: ...ault address of 00110102 independent of the status of the CONFIG pin All of the LM49360 s I2C chip addresses are selectable via I2C registers 0x40h and 0x41h in the PMU register space 22 3 I2C DATA VA...

Page 40: ...ck acknowledge SDA pulled down by slave rs repeated start FIGURE 10 Example I2C Write Cycle When a READ function is to be accomplished a WRITE function must precede the READ function as shown in the R...

Page 41: ...5 Data Hold Time Input direction delay generated by the Master 0 900 ns 6 Data Setup Time 100 ns 7 Rise Time of SDA and SCL 20 0 1CB 300 ns 8 Fall Time of SDA and SCL 15 0 1CB 300 ns 9 Set up Time for...

Page 42: ...the shutdown sequence PS_HOLD needs to be held low greater than 30ms before RESET_N is asserted low The PMU then starts the shutdown sequence in the opposite order of the startup sequence Note 3 If PS...

Page 43: ...conditions Buck startup duration is typically 40 s LDO startup duration is typically 50 s and LDO7 HILO startup duration is typically 70 s For details please see LDOs and BUCK electrical specification...

Page 44: ...CK are enabled disabled Enabling disabling process duration depends on voltages and loading conditions Buck startup duration is typically 40 s LDO startup duration is typically 50 s and LDO7 HILO star...

Page 45: ...re are valid if there the registers are not rewritten via I2C Note 2 The timing showed here define time points when LDOs and BUCK are enabled disabled Enabling disabling process duration depends on vo...

Page 46: ...hen this output turn on after tS 7 Note 5 Upon initial power up the PMU registers are loaded with default values Changes to the default values will be retained until device power is removed Register v...

Page 47: ...LDO2 0x99h LDO2_DLY LDO2_VSEL 0x16h LDO3 0x79h LDO3_DLY LDO3_VSEL 0x17h LDO4 0xACh LDO4_DLY LDO4_VSEL 0x18h LDO5 0x99h LDO5_DLY LDO5_VSEL 0x19h LDO6 0x99h LDO6_DLY LDO6_VSEL 0x1Ah LDO7 0x07h LDO7_DLY...

Page 48: ...PD RSVD TIMESTEP UVLO_VSEL 0x3Ch PLDWN 0xFFh LDO6_PD LDO5_PD LDO4_PD LDO3_PD LDO2_PD LDO1_PD BK2PD BK1PD 0x3Dh OVR 0x00h LDO7OV R LDO6OVR LDO5OVR LDO4OVR LDO3OVR LDO2OVR LDO1OVR BK1OVR I2C DEVICE ADDR...

Page 49: ...CLK_SEL MUTE_R MUTE_L DAC_OSR 0x31h DAC _CLOCK DAC_CLK_DIV S DIGITAL MIXER 0x40h IPLVL1 PORT2_RX_R_LVL PORT2_RX_L_LVL PORT1_RX_R_LVL PORT1_RX_L_LVL 0x41h IPLVL2 INTERP_L_LVL INTERP_R_LVL ADC_R_LVL ADC...

Page 50: ...0x82h ADC NG_ENB NOISE_FLOOR ALC 2 0x83h ADC ALC_TARGET_LEVEL ALC 3 0x84h ADC ATTACK_RATE ALC 4 0x85h ADC PK_DECAY_RATE DECAY_RATE RELEASE_RATE ALC 5 0x86h ADC HOLDTIME ALC 6 0x87h ADC MAX_LEVEL ALC 7...

Page 51: ...5 LEVEL FREQ 0xB0h SOFTCLIP 1 SOFT KNEE THRESHOLD 0xB1h SOFTCLIP 2 RATIO 0xB2h SOFTCLIP 3 LEVEL DAC EFFECT MONITORS 0xB8h LVLMONL DAC LEFT LEVEL MONITOR 0xB9h LVLMONR DAC RIGHT LEVEL MONITOR 0xBAh FXC...

Page 52: ...the CONFIG pin 01 Force Bank 0 CAM 10 Force Bank 1 SUB_PMU 11 Force Bank 2 AP_PMU 7 SWOVR If SWOVR Software Override is set it allows PMU outputs to be enabled under I2C control of the SWOVR Software...

Page 53: ...filter is bypassed Set this bit high for 1ms after changing VSEL if the output voltage needs to be adjusted while the LDO is enabled Otherwise the internal filter will slow the transition time to ove...

Page 54: ...tage ambient temperature and the inductor chosen There are two modes of operation depending on the current required PWM Pulse Width Modulation ECO ECOnomy mode The device operates in PWM mode at load...

Page 55: ...limit of the PMOS is exceeded Then the NMOS switch is turned on and the inductor current ramps down The next cycle is initiated by the clock turning off the NMOS and turning on the PMOS 30128232 FIGU...

Page 56: ...5 99 Buck Output Voltage Selection The selection of the bucks output voltages can be done by writing a specific code into the control registers addr 0x12 0x22 0x32 for Buck1 addr 0x13 0x23 0x33 for Bu...

Page 57: ...nected to the output with the recommended value of 1 F It is important that the capacitance is within the specified value across voltage and temperature PMU Enabled The PMU allows four major methods o...

Page 58: ...7 Bank 2 CONFIG L 0x3Dh bits 0 7 The OVR register bit for Buck 2 is located in the following ENB2 registers Bank 0 CONFIG Z 0x11h bit 7 Bank 1 CONFIG H 0x21h bit 7 Bank 2 CONFIG L 0x31h bit 7 The SUB...

Page 59: ...ET_N CONFIG H 0x2Eh PMU Thermal Shutdown TSD The PMU registers that support the TSD are listed in the table below See individual register descriptions for the details I2C Register Name I2C Register Ad...

Page 60: ...fast discharging of output capacitors in shut down the LDO7 HILO can connect a 300 pull down resistor to the output This resistor is only connected when the LDO is disabled See Table 20 for the regist...

Page 61: ...s Field Description 3 0 LDO7_VSEL Selects the output voltage LDO _VSEL Vout V LDO _VSEL Vout V 0000 1 55 1000 1 15 0001 1 5 1001 1 1 0010 1 45 1010 1 05 0011 1 4 1011 1 0100 1 35 1100 0 95 0101 1 3 11...

Page 62: ...2 output will be pulled down by a 300 resistor when disabled 2 LDO1_PD If set the LDO1 output will be pulled down by a 300 resistor when disabled 3 LDO2_PD If set the LDO2 output will be pulled down b...

Page 63: ...or TSDL 110 0 111 1 3 BK1_SUBOVR If set the Buck1 output enables when SUBOVR is set i e PS_HOLD in a subPMU mode 4 LDO1_SUBOVR If set the LDO1 output enables when SUBOVR is set i e PS_HOLD in a subPMU...

Page 64: ...11 1111110 100 1111001 101 1111000 110 1111011 111 1111010 5 3 AUD_I2C_ADDR The I2C Address for the Audio Subsystem AUD_I2C_ADDR I2C_ADDR 000 0011010 001 0011011 010 0011000 011 0011001 100 0011110 10...

Page 65: ...es the oscillator can be used instead of an external system clock to drive the chip s power management PMC OSC_ENABLE Oscillator Status 0 Oscillator Off 1 Oscillator On 4 MCLK_OVR This forces the MCLK...

Page 66: ...egister is used to control the LM49360 s Power Management Circuit Clock Divider TABLE 29 PMC_SETUP 0x02h Bits Field Description 7 0 PMC_CLK_DIV This programs the half cycle divider that precedes the P...

Page 67: ...sed the PLL input clock can come from three sources The clock input to the PLL can come from the MCLK input the PORT1_CLK input or the PORT2_CLK input The LM49360 s Power Management Circuit PMC requir...

Page 68: ...30128213 FIGURE 20 Internal Clock Network 67 www ti com LM49360...

Page 69: ...s dual audio ports The PLL has a P1 and P2 output divider thereby allowing the PLL to generate two distinct clock outputs The equations for the PLL s generated output clocks are as follows fOUT1 fIN N...

Page 70: ...00 0 19 68 20 5 147 0 12 5 11289600 0 19 8 27 5 196 0 12 5 11289600 0 26 18 5 144 19 18 11289602 1 2 1 27 37 5 196 0 12 5 12289600 0 11 2896 10 5 195 0 17 5 12000000 0 12 288 8 125 0 16 12000000 0 13...

Page 71: ...grams the PLL s M divider to divide from 1 to 64 PLL_M PLL Input Divider Value 000000 1 000001 1 000010 1 5 000011 2 000100 2 5 000101 3 1111101 63 1111110 63 5 1111111 64 TABLE 35 PLL_N 0x05h Bits Fi...

Page 72: ...1 0x07h Bits Field Description 7 0 PLL_P1 7 0 This programs the 8 LSBs of the PLL s P1 Divider These LSBs combine with PL1_P1 8 which allows the P1 divider to divide by up to 256 PLL_P1 8 0 P1 Divider...

Page 73: ...the speaker and associated cables and traces Where a fixed frequency class D exhibits large amounts of spectral energy at multiples of the switching frequency the spread spectrum architecture of the L...

Page 74: ...rformance Charge Pump Flying Capacitor C38 The flying capacitor C38 affects the load regulation and output impedance of the charge pump A C38 value that is too low results in a loss of current drive l...

Page 75: ...low current drive mode where the AUXOUT amplifier operates in a power saving mode AUX_LINE_OUT Mode to provide a differential output that is used as a mono differential line level input to a standalon...

Page 76: ...8dB 0010 10dB 0011 12dB 0100 14dB 0101 16dB 0110 18dB 0111 20dB 1000 22dB 1001 24dB 1010 26dB 1011 28dB 1100 30dB 1101 32dB 1110 34dB 1111 36dB 4 SE_DIFF If set the MIC negative input is ignored In s...

Page 77: ...0 37 5dB 100110 10 5dB 000111 36dB 100111 12dB 001000 34 5dB 101000 13 5dB 001001 33dB 101001 15dB 001010 31 5dB 101010 16 5dB 001011 30dB 101011 18dB 001100 28 5dB 001101 27dB 001110 25 5dB 001111 24...

Page 78: ...36dB 100111 12dB 001000 34 5dB 101000 13 5dB 001001 33dB 101001 15dB 001010 31 5dB 101010 16 5dB 001011 30dB 101011 18dB 001100 28 5dB 001101 27dB 001110 25 5dB 001111 24dB 010000 22 5dB 010001 21dB...

Page 79: ...each headphone amplifier output Without the presence of a headphone plug the headphone jack s mechanical switch is closed thereby connecting the right headphone amplifier output to RPU The GPIO pin d...

Page 80: ...s bit enables the headphone sense circuit If enabled the headphone amplifier will automatically turn on off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone sense inpu...

Page 81: ...CLK_SEL Source 000 MCLK 001 PORT1_RX_CLK 010 PORT2_RX_CLK 011 PLL_OUTPUT1 100 PLL_OUTPUT2 7 ADC_DSP_ONLY If set the ADC s analog circuitry is disabled to reduce power consumption however ADC DSP funct...

Page 82: ...channel ADC_MIX_LEVEL_L Level 00 0dB 01 1 35dB 10 3 5dB 11 6dB 3 2 ADC_MIX_LEVEL_R This sets the input level to the right ADC channel ADC_MIX_LEVEL_R Level 00 0dB 01 1 35dB 10 3 5dB 11 6dB 4 STEREO_LI...

Page 83: ...L_OUTPUT1 100 PLL_OUTPUT2 7 DSP_ONLY If set the DAC s analog circuitry is disabled to reduce power consumption however DAC DSP functionality is maintained This can be used to perform asynchronous re s...

Page 84: ...version SRC between audio ports This allows simultaneous operation of the dual audio ports even if each port is operating at a different sample rate The LM49360 can be used as an audio port bridge wit...

Page 85: ...nnel of Audio Port 2 PORT2_RX_L_LVL Level 00 0dB 01 6dB 10 12dB 11 18dB 7 6 PORT2_RX_R _LVL This programs the input level of the data arriving from the right receive channel of Audio Port 2 PORT2_RX_R...

Page 86: ...R 10 PORT2_RX_R 11 DAC_INTERP_R 4 SWAP If set this swaps the Left and Right outputs to Audio Port 1 5 MONO If set the right channel is ignored and the left channel becomes left right 2 TABLE 57 Audio...

Page 87: ...and Right inputs to the DAC TABLE 59 Decimator Input Select 0x45h Bits Field Description 1 0 L_SEL This selects which input is fed to the left ADC s decimator input L_SEL Selected Input 00 None 01 POR...

Page 88: ...URE 24 I2S Serial Data Format 24 bit example 30128272 FIGURE 25 Left Justified Data Format 24 bit example 30128270 FIGURE 26 Right Justified Data Format 24 bit example 30128234 FIGURE 27 PCM Serial Da...

Page 89: ...301282i1 FIGURE 28 Timing for I2S Master 301282i2 FIGURE 29 Timing for I2S Slave www ti com 88 LM49360...

Page 90: ...X on rising edge RX on falling edge 6 STEREO_SYNC_PHASE If set this reverses the left and right channel data of the Audio Port STEREO_SYNC_PHASE Audio Port Data Orientation 0 Left channel data goes to...

Page 91: ...M Along with SYNTH_NUM this sets the clock divider that generates the Port 1 or Port 2 clock in master mode SYNTH_DENOM Denominator 0 128 1 125 TABLE 63 CLK_GEN_1 0x53h 63h Bits Field Description 2 0...

Page 92: ...tion 2 0 RX_WIDTH This programs the expected bits per word of the serial data input SDI RX_WIDTH Bits 000 24 001 20 010 18 011 16 100 14 101 13 110 12 111 8 5 3 TX_WIDTH This programs the bits per wor...

Page 93: ...LSB Justified MSB_POSITION Description 00000 0 Left Justified PCM Long 00001 1 I2S PCM Short 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110...

Page 94: ...SB Justified MSB_POSITION Description 00000 0 Left Justified PCM Long 00001 1 I2S PCM Short 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14...

Page 95: ...ALC digital soft clip compression and a 5 band parametric EQ The ADC DSP features digital volume control automatic level control ALC and digital soft clip compression The effects chain of each DSP en...

Page 96: ...iption 0 DAC_ALC_ENB This enables the DAC s Automatic Level Control 1 DAC_PK_ENB This enables the DAC s Peak Detector 2 DAC_EQ_ENB This enables the DAC s 5 band Parametric EQ 3 RSVD Reserved 4 ADC_SCL...

Page 97: ...idered as noise and will be gated from the ALC s peak detector in order to avoid noise pumping So it is important to set NOISE_FLOOR to correlate with the signal to noise ratio of the corresponding au...

Page 98: ...lifier or ADC in order to prevent harsh distortions delivered to the loudspeaker or headphone on the receiving end This method of ALC limiter operation is also known as no clip mode Operating the ALC...

Page 99: ...stereo imaging If this bit is cleared then both channels operate as dual mono 5 SOURCE_RSEL If both SOURCE_OVR and this bit is set the right ADC ALC channel will be active 6 SOURCE_LSEL If both SOURC...

Page 100: ...l be attenuated TARGET_LEVEL Target Level dB 00000 1 5 00001 3 00010 4 5 00011 6 00100 7 5 00101 9 00110 10 5 00111 12 01000 13 5 01001 15 01010 16 5 01011 18 01100 19 5 01101 21 01110 22 5 01111 24 1...

Page 101: ...eps s 00000 21 00001 42 00010 83 00011 167 00100 250 00101 333 00110 417 00111 542 01000 729 01001 958 01010 1250 Default 01011 1604 01100 1896 01101 2208 01110 2792 01111 3708 10000 4792 10001 5688 1...

Page 102: ...8 01000 896 01001 1250 01010 1396 Default 01011 2000 01100 2708 01101 3500 01110 4750 01111 6250 10000 8000 10001 11000 10010 14000 10011 18500 10100 25000 10101 32000 10110 42000 10111 55000 11000 72...

Page 103: ...500 11100 640 11101 800 11110 1000 11111 1250 TABLE 76 ADC_ALC_7 0x87h Bits Field Description 5 0 MAX_LEVEL This sets the maximum allowed gain of the volume control to the output amplifier whenever th...

Page 104: ...101010 13 5dB 001011 60dB 101011 12dB 001100 58 5dB 101100 10 5dB 001101 57dB 101101 9dB 001110 55 5dB 101110 7 5dB 001111 54dB 101111 6dB 010000 52 5dB 110000 4 5dB 010001 51dB 110001 3dB 010010 49 5...

Page 105: ...1 63dB 101001 15dB 001010 61 5dB 101010 13 5dB 001011 60dB 101011 12dB 001100 58 5dB 101100 10 5dB 001101 57dB 101101 9dB 001110 55 5dB 101110 7 5dB 001111 54dB 101111 6dB 010000 52 5dB 110000 4 5dB 0...

Page 106: ...ressor threshold level THRESHOLD by a fixed ratio com pressor output compressor input that is set by a predetermined audio compression ratio RATIO Higher compression ratios result in more compression...

Page 107: ...udio signal beyond the compressor threshold To achieve the smoothing effect to prevent hard clipping the soft knee function initially compresses the audio signal at the smallest ratio and then increme...

Page 108: ...B 0111 15dB 1000 14dB 1001 12dB 1010 10dB 1011 8dB 1100 6dB 1101 4dB 1110 2 5dB 1111 1dB 4 SOFT_KNEE If set the audio compressor will automatically apply higher compression ratios to audio signals hig...

Page 109: ...00 1 1 Bypass 00001 1 1 2 00010 1 1 4 00011 1 1 7 00100 1 2 0 00101 1 2 4 00110 1 2 8 00111 1 3 4 01000 1 4 0 01001 1 4 7 01010 1 5 7 01011 1 6 7 01100 1 8 0 01101 1 9 5 01110 1 11 3 01111 1 13 5 1000...

Page 110: ...11 18dB 00100 16 5dB 00101 15dB 00110 13 5dB 00111 12dB 01000 10 5dB 01001 9dB 01010 7 5dB 01011 6dB 01100 4 5dB 01101 3dB 01110 1 5dB 01111 0dB 10000 1 5dB 10001 3dB 10010 4 5dB 10011 6dB 10100 7 5dB...

Page 111: ...um gain that the ALC will apply Care should be taken when choosing the optimum I2C gain setting whenever enabling the Limiter 4 STEREO LINK If set the ALC circuit uses the stereo average of the input...

Page 112: ...attenuated TARGET_LEVEL Target Level dB 00000 1 5 00001 3 00010 4 5 00011 6 00100 7 5 00101 9 00110 10 5 00111 12 01000 13 5 01001 15 01010 16 5 01011 18 01100 19 5 01101 21 01110 22 5 01111 24 10000...

Page 113: ...teps us 00000 21 00001 42 00010 83 00011 167 00100 250 00101 333 00110 417 00111 542 01000 729 01001 958 01010 1250 Default 01011 1604 01100 1896 01101 2208 01110 2792 01111 3708 10000 4792 10001 5688...

Page 114: ...10001 11000 10010 14000 10011 18500 10100 25000 10101 32000 10110 42000 10111 55000 11000 72500 11001 100000 11010 125000 11011 160000 11100 225000 11101 300000 11110 375000 11111 500000 0 5s 7 5 PK_D...

Page 115: ...0 25 01111 32 10000 40 10001 50 10010 64 10011 80 10100 100 10101 125 10110 160 10111 200 11000 250 11001 320 11010 400 11011 500 11100 640 11101 800 11110 1000 11111 1250 TABLE 89 DAC_ALC_7 0xA6h Bit...

Page 116: ...5dB 001011 60dB 101011 12dB 001100 58 5dB 101100 10 5dB 001101 57dB 101101 9dB 001110 55 5dB 101110 7 5dB 001111 54dB 101111 6dB 010000 52 5dB 110000 4 5dB 010001 51dB 110001 3dB 010010 49 5dB 110010...

Page 117: ...01 15dB 001010 61 5dB 101010 13 5dB 001011 60dB 101011 12dB 001100 58 5dB 101100 10 5dB 001101 57dB 101101 9dB 001110 55 5dB 101110 7 5dB 001111 54dB 101111 6dB 010000 52 5dB 110000 4 5dB 010001 51dB...

Page 118: ...gain at fC LEVEL Effect 00000 Off 0dB 00001 15dB 00010 14dB 00011 13dB 00100 12dB 00101 11dB 00110 10dB 00111 9dB 01000 8dB 01001 7dB 01010 6dB 01011 5dB 01100 4dB 01101 3dB 01110 2dB 01111 1dB 10000...

Page 119: ...5dB 00010 14dB 00011 13dB 00100 12dB 00101 11dB 00110 10dB 00111 9dB 01000 8dB 01001 7dB 01010 6dB 01011 5dB 01100 4dB 01101 3dB 01110 2dB 01111 1dB 10000 0dB 10001 1dB 10010 2dB 10011 3dB 10100 4dB 1...

Page 120: ...dB 00010 14dB 00011 13dB 00100 12dB 00101 11dB 00110 10dB 00111 9dB 01000 8dB 01001 7dB 01010 6dB 01011 5dB 01100 4dB 01101 3dB 01110 2dB 01111 1dB 10000 0dB 10001 1dB 10010 2dB 10011 3dB 10100 4dB 10...

Page 121: ...15dB 00010 14dB 00011 13dB 00100 12dB 00101 11dB 00110 10dB 00111 9dB 01000 8dB 01001 7dB 01010 6dB 01011 5dB 01100 4dB 01101 3dB 01110 2dB 01111 1dB 10000 0dB 10001 1dB 10010 2dB 10011 3dB 10100 4dB...

Page 122: ...gain at fC LEVEL Effect 00000 Off 0dB 00001 15dB 00010 14dB 00011 13dB 00100 12dB 00101 11dB 00110 10dB 00111 9dB 01000 8dB 01001 7dB 01010 6dB 01011 5dB 01100 4dB 01101 3dB 01110 2dB 01111 1dB 10000...

Page 123: ...B 0111 15dB 1000 14dB 1001 12dB 1010 10dB 1011 8dB 1100 6dB 1101 4dB 1110 2 5dB 1111 1dB 4 SOFT_KNEE If set the audio compressor will automatically apply higher compression ratios to audio signals hig...

Page 124: ...000 1 1 Bypass 00001 1 1 2 00010 1 1 4 00011 1 1 7 00100 1 2 0 00101 1 2 4 00110 1 2 8 00111 1 3 4 01000 1 4 0 01001 1 4 7 01010 1 5 7 01011 1 6 7 01100 1 8 0 01101 1 9 5 01110 1 11 3 01111 1 13 5 100...

Page 125: ...011 18dB 00100 16 5dB 00101 15dB 00110 13 5dB 00111 12dB 01000 10 5dB 01001 9dB 01010 7 5dB 01011 6dB 01100 4 5dB 01101 3dB 01110 1 5dB 01111 0dB 10000 1 5dB 10001 3dB 10010 4 5dB 10011 6dB 10100 7 5d...

Page 126: ...E out 010001 EP ENABLE out 010010 EP ENABLE out 010011 ADC CLIPPED out 010100 ADC CLIPPED out 010101 DAC CLIPPED out 010110 DAC CLIPPED out 010111 SOMETHING CLIPPED out 011000 SOMETHING CLIPPED out 01...

Page 127: ...SET Setting this bit resets the digital core of LM49360 SOFT_RESET does not affect the current I2C register settings TABLE 104 Spread Spectrum 0xF1h Bits Field Description 1 0 RSVD Reserved 2 SS_DISAB...

Page 128: ...40 0 Schematic Diagram 30128220 FIGURE 36 Demo Board Schematic 127 www ti com LM49360...

Page 129: ...30128245 FIGURE 37 Demo Board Schematic www ti com 128 LM49360...

Page 130: ...41 0 Demonstration Board Layout 30128243 FIGURE 38 Top Silkscreen 30128244 FIGURE 39 Top Layer 129 www ti com LM49360...

Page 131: ...30128238 FIGURE 40 Inner Layer 2 30128239 FIGURE 41 Inner Layer 3 www ti com 130 LM49360...

Page 132: ...30128240 FIGURE 42 Inner Layer 4 30128241 FIGURE 43 Inner Layer 5 131 www ti com LM49360...

Page 133: ...30128231 FIGURE 44 Bottom Layer 30128242 FIGURE 45 Bottom Silkscreen www ti com 132 LM49360...

Page 134: ...42 0 Revision History Rev Date Description 1 0 11 14 11 Initial WEB released 1 01 12 01 11 Changed the Vdo Max limit in the EC LDOs 1 to 6 table from 200 to 250 133 www ti com LM49360...

Page 135: ...3 0 Physical Dimensions inches millimeters unless otherwise noted micro SMD 64 Package Order Number LM49360RL NS Package Number RLA64JBA X1 4 169 03mm X2 3 99 03mm X3 0 65 075mm www ti com 134 LM49360...

Page 136: ...Notes 135 www ti com LM49360...

Page 137: ...or use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have...

Search results

Summary of Contents for Boomer LM49360

Reviews:

Brands by name

Popular brands

Texas Instruments Boomer LM49360, User Manual

Search results

Summary of Contents for Boomer LM49360

Reviews:

Brands by name

Popular brands