Texas Instruments Boomer LM49360, User Manual

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33.0 ADC Control Registers
This register is used to control the LM49360's ADC:
TABLE 49. ADC Basic (0x20h)
Bits Field Description
0 MONO This sets mono or stereo operation of the ADC.
MONO ADC Operation
0 Stereo Audio
1 Mono Voice (Right ADC channel disabled, Left ADC channel active)
1 OSR This sets the oversampling ratio of the ADC.
OSR
Stereo Audio ADC
Oversampling Ratio
Mono Voice ADC Oversampling Ratio
0 128 125
1 128 128
2 MUTE_L If set, a digital mute is applied to the Left (or mono) ADC output.
3 MUTE_R If set, a digital mute is applied to the Right ADC output.
6:4 ADC_CLK_SEL This selects the source of the ADC clock domain, ADC_SOURCE_CLK.
ADC_CLK_SEL Source
000 MCLK
001 PORT1_RX_CLK
010 PORT2_RX_CLK
011 PLL_OUTPUT1
100 PLL_OUTPUT2
7 ADC_DSP_ONLY If set, the ADC's analog circuitry is disabled to reduce power consumption, however, ADC DSP
functionality is maintained. This can be used to perform asynchronous re-sampling between audio
rates of a common family. Setting this bit is also useful whenever applying Automatic Level Control
(ALC) to an analog only audio path.
TABLE 50. ADC_CLK_DIV (0x21h)
Bits Field Description
7:0 ADC_CLK_DIV This programs the half cycle divider that precedes the ADC. The input of this divider should be
around 12MHz. The default of this divider is 0x00.
Program this divider with the division you want, multiplied by 2, and subtract 1.
ADC_CLK_DIV Divides by
00000000 1
00000001 1
00000010 1.5
00000011 2
— —
11111101 127
11111110 127.5
11111111 128
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