background image

C5

C6

C2

C1

C3

C4

-V

CC

+V

CC

U1

+

-

R

OUT

C

L

OUT

R

F

-V

CC

1

1

3

2

4

5

R

G

R

T

+IN

-IN

R

IN

+V

CC

1

Non-Inverting gain:  1+

R

F

R

G

 + R

T

User's Guide

SNOA492A – July 2007 – Revised April 2013

AN-1662 LMV551 Evaluation Board

1

Introduction

The 551013116-001 evaluation board, is designed to aid in the characterization of Texas Instruments
LMV551 3 MHz, low voltage, low power, RR output op amp, that is available in the 5-Pin SC70 package.
The board layout allows for either inverting gain or non-inverting gain configurations. Use the evaluation
board as a:

Guide to high frequency layout

Tool to aid in device testing and characterization

2

Basic Operation

Figure 1

shows the basic configuration that allows either inverting gain or non-inverting gain operation.

The input signal is brought into the board through SMA connectors for either the inverting or non-inverting
input of the amplifier.

For non-inverting operation, the closed-loop gain is:

(1)

The value of the feedback resistor, R

F

, has a strong influence on AC performance.

Figure 1. Evaluation Board Schematic

All trademarks are the property of their respective owners.

1

SNOA492A – July 2007 – Revised April 2013

AN-1662 LMV551 Evaluation Board

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Copyright © 2007–2013, Texas Instruments Incorporated

Summary of Contents for AN-1662 LMV551

Page 1: ...s a Guide to high frequency layout Tool to aid in device testing and characterization 2 Basic Operation Figure 1 shows the basic configuration that allows either inverting gain or non inverting gain operation The input signal is brought into the board through SMA connectors for either the inverting or non inverting input of the amplifier For non inverting operation the closed loop gain is 1 The va...

Page 2: ...ncy performance When designing your own board use the evaluation board as a guide and follow these steps as a basis for high frequency layout 1 Use a ground plane 2 Include 6 8 μF tantalum C1 C2 and 0 1 μF ceramic C3 C6 capacitors on both supplies 3 Place the 6 8 μF capacitors within 0 75 inches of the power pins 4 Place the 0 1 μF capacitors less than 0 1 inches from the power pins 5 Place 0 01 μ...

Page 3: ...www ti com Evaluation Board Figure 3 Layer 2 3 SNOA492A July 2007 Revised April 2013 AN 1662 LMV551 Evaluation Board Submit Documentation Feedback Copyright 2007 2013 Texas Instruments Incorporated ...

Page 4: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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