EMIF
Table 7-99. IBANK, RSIZE and PAGESIZE Fields Information (continued)
Bit Field
Bit Value
Bit Description
Defines the page size of each page of the external DDR2/3/mDDR memory device
0
256 words (requires 8 column address bits)
PAGESIZE
1h
512 words (requires 9 column address bits)
2h
1024 words (requires 10 column address bits)
3h
2048 words (requires 11 column address bits)
Defines the number of internal banks on the external DDR2/3/mDDR memory device
0
1 bank
IBANK
1h
2 banks
2h
4 banks
3h
8 banks
Defines the number of DDR2/3/mDDR memory controller chip selects
EBANK
0
CS0 only
1h
Reserved
When addressing SDRAM, if the REG_IBANK_POS field in the SDRAM Config register is set to 0, and the
REG_EBANK_POS field in the SDRAM Config 2 register is also set to 0, the DDR2/3/mDDR memory
controller uses the three fields, IBANK, EBANK and PAGESIZE in the SDRAM Config register to
determine the mapping from source address to SDRAM row, column, bank, and chip select. If the
REG_IBANK_POS field in the SDRAM Config register is set to 1, 2, or 3, or the REG_EBANK_POS field
in the SDRAM Config 2 register is set to 1, the DDR2/3/mDDR memory controller uses the 4 fields -
IBANK, EBANK, PAGESIZE, and ROWSIZE in the SDRAM Config register to determine the mapping from
source address to SDRAM row, column, bank, and chip select. In all cases the DDR2/3/mDDR memory
controller considers its SDRAM address space to be a single logical block regardless of the number of
physical devices or whether the devices are mapped across 1 or 2 DDR2/3/mDDR memory controller chip
selects.
7.3.3.4.1 Address Mapping when REG_IBANK_POS=0 and REG_EBANK_POS=0
For REG_IBANK_POS=0 and REG_EBANK_POS=0, the effect of address mapping scheme is that as the
source address increments across DDR2/3/mDDR memory device page boundaries, the DDR2/3/mDDR
controller moves onto the same page in the next bank in the current device DDR_CSn[0]. This movement
along the banks of the current proceeds to the same page in the next device(if EBANK=1, DDR_CSn[1])
and proceeds through the same page in all its banks before moving over to the next page in the first
device(DDR_CSn[0]). The DDR2/3/mDDR controller exploits this traversal across internal banks and chip
selects while remaining on the same page to maximize the number of open DDR2/3/mDDR memory
device banks within the overall DDR2/3/mDDR memory device space.
Thus, the DDR2/3/mDDR controller can keep a maximum of 16 banks (8 internal banks across 2 chip
selects) open at a time, and can interleave among all of them.
Table 7-100. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=0 and
REG_EBANK_POS=0
Logical Address
Row Address
Chip Select
Bank Address
Column Address
# of bits defined by EBANK of
# of bits defined by IBANK of
# of bits defined by PAGESIZE
SDRCR
SDRCR
of SDRCR
15 bits
EBANK=0 => 0 bits
IBANK=0 => 0 bits
PAGESIZE=0 => 8 bits
EBANK=1 => 1 bit
IBANK=1 => 1 bit
PAGESIZE=1 => 9 bits
IBANK=2 => 2 bits
PAGESIZE=2 => 10 bits
IBANK=3 => 3 bits
PAGESIZE=3 => 11 bits
410 Memory Subsystem
SPRUH73H – October 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated