Basic Test Procedure
Figure 7. TSW1400 Multitone Pattern
3.4
AFE7070 Software Quick-Start Guide
•
In the
Clock Settings
section, set the clock mode to
Dual Input Clock
.
•
If the LVDS output is not connected to anything, disable it using the
LVDS Power Down
switch under
the
Power
heading.
•
Select the CDCM7005 tab to adjust the output clock signals:
–
Y1 (AFE7070’s CLK_IO) must be LVCMOS, with Y1A set to active rather than 3-state.
–
Y3 (AFE7070’s DACCLK) must be LVPECL, with both Y3A and Y3B set to active.
–
Y4 (CDC Out) must be LVCMOS, with Y4A set to active.
•
Press the
Send All
button in the
Register Controls
section.
•
Monitor the RF output signal on a spectrum analyzer.
•
Monitor the output signal at the RF output connector. If the LO input frequency is set to 2.1 GHz and
the digital inputs are configured to be tones at 4.5 MHz and 5.5 MHz, the RF output looks like two
tones placed at 2004.5 MHz and 2005.5 MHz as seen in
.
If no output is observed on the spectrum analyzer, reset the AFE7071 by pressing the SW1 switch on the
AFE7071 EVM.
10
AFE707xEVM Evaluation Module
SLOU337A – March 2012 – Revised July 2015
Copyright © 2012–2015, Texas Instruments Incorporated
