EVM Headers, Test Points, and Configuration
34
SLOU430A – December 2015 – Revised February 2016
Copyright © 2015–2016, Texas Instruments Incorporated
Hardware Configuration
Figure 50. EVM ADC Clock Source Configuration Examples
Configuration 1 (LVDS Only):
To use the on-board single-ended crystal oscillator as the clock source for
the AFE, connect shunt jumpers for configuration 1 (as seen in
). Use this configuration for LVDS
Data output only, not JESD204B. Note: J37 powers the on-board oscillator with 3.3 V, due to the power
limitations of the VCC1-3B3-40M0000 low-jitter crystal oscillator. The recommended ADC clock input for
new designs is to use low-jitter square signals (LVCMOS levels, 1.8-V amplitude.)
Configuration 2 (LVDS Only):
To use the differential direct external clock as the clock source for the
AFE, connect shunt jumpers for configuration 2. Use this configuration for LVDS Data output only, not
JESD204B. Also, connect a single-ended external clock generator to SMA J35. Set the clock source to an
appropriate frequency, such as 10 MHz to 80 MHz, and +15-dBm amplitude.
Configuration 3 (Default):
This mode uses an on-board crystal to stimulate the LMK04826 in Dual-PLL
mode. To use the differential outputs from the LMK04826 as the clock source for the AFE, connect shunt
jumpers for configuration 3. Ensure that jumper J29 is installed.
Configuration 4:
This mode uses an external generator at J32 to stimulate the LMK04826 in Clock
Distribution mode. To use the differential outputs from the LMK04826 as the clock source for the AFE,
connect shunt jumpers for configuration 4. Also, connect an external clock generator to J32. Set the clock
source to 400 MHz, and +15-dBm amplitude. Consult a TI engineer to use this mode.
