EVM Circuit Description
2
EVM Circuit Description
The complete schematic of the EVM can be found at the end of this user guide. Critical portions of the
EVM are explained in the following text.
2.1
Power
The EVM requires a single 5-V supply for operation that can be supplied through banana jacks. Separate
LDOs convert the 5-V input to generate the 3.3-V AVDD supply and the 1.8-V LVDD supply required for
the ADS5263 operation.
2.2
Clock Input
The clock can be supplied to the analog-to-digital converter (ADC) in one of two ways. The default
factory-configured option supplies a single-ended sine wave clock directly to the SMA connecter J31. This
clock is converted to differential by the TC4-1W transformer from MiniCircuits and is ac coupled to the
ADC. This transformer has an impedance ratio of 4, so the voltage applied on J31 is stepped up by a
factor of 2.
The clock input must be from a clean, low-jitter source (such as SMA100A or 8644B) and filtered by a
narrow band-pass filter. Taking into account the attenuation of the filter, the clock amplitude must be set
appropriately to get about 1.5-V peak-to-peak at the clock pins of the ADS5263.
The clock source is commonly synchronized with the signal generator of the input frequency to keep the
clock and input coherent for meaningful FFT analysis.
Figure 2. AD5263 Sine Wave Clocking Using Transformer
LVPECL Clock Option
Alternately, the clock may be supplied by an onboard LVPECL clock buffer (TI
’
s CDCLVP1102). To use
this option,
•
Remove the coupling capacitors C59, C61.
•
Replace the 0-
Ω
resistors with 0.1-
µ
F capacitors.
•
Apply a single-ended, square-wave clock signal on SMA connector J33.
3
SLAU344
–
May 2011
ADS5263EVM Evaluation Module
Copyright
©
2011, Texas Instruments Incorporated