Texas Instruments ADS1278-SP, User Manual, Page: 18 / 32

ADS1278EVM-CVAL Hardware Details
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18 SBAU324 – September 2018
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ADS1278EVM-CVAL Evaluation Module User's Guide
Analog input sources (Channels 5-8) are connected directly to J1 . These inputs can be filtered by
installing passive components in the option filter circuitry. By default, the resistors are populated with 0- Ω
resistors and the capacitors are not installed. No circuitry is provided to buffer these signals before
connecting to the converter.
(1)
Pin 1 is top left-hand corner, located next to reference designator.
Table 7. J3: Primary Analog Interface Pinout
Description Signal Designator Signal Description
Analog Input Channel 4 Negative AINN4 J3.1
(1)
J3.2 AINP4 Analog Input Channel 4 Positive
Analog Input Channel 3 Negative AINN3 J3.3 J3.4 AINP3 Analog Input Channel 3 Positive
Analog Input Channel 2 Negative AINN2 J3.5 J3.6 AINP2 Analog Input Channel 2 Positive
Analog Input Channel 1 Negative AINN1 J3.7 J3.8 AINP1 Analog Input Channel 1 Positive
Analog Ground AGND J3.9 J3.10 Not Connected Not used for this design
Analog Ground AGND J3.11 J3.12 Analog Ground AGND
Analog Ground AGND J3.13 J3.14 Not Connected Not used for this design
Not used for this design Not Connected J3.15 J3.16 Not Connected Not used for this design
Analog Ground AGND J3.17 J3.18 EXTREFN External Reference negative input
Analog Ground AGND J3.19 J3.20 EXTREFP External Reference positive input
(1)
Pin 1 is top right-hand corner, located next to reference designator.
Table 8. J1: Secondary Analog Interface Pinout
Description Signal Designator Signal Description
Not used for this design Not Connected J1.1
(1)
J1.2 Not Connected Not used for this design
Analog Input Channel 8 Negative AINN8 J1.3 J1.4 AINP8 Analog Input Channel 8 Positive
Analog Input Channel 7 Negative AINN7 J1.5 J1.6 AINP7 Analog Input Channel 7 Positive
Analog Input Channel 6 Negative AINN6 J1.7 J1.8 AINP6 Analog Input Channel 6 Positive
Analog Input Channel 5 Negative AINN5 J1.9 J1.10 AINP5 Analog Input Channel 5 Positive
5.5 Digital Interface
The digital signals are controlled via DSP interface or I
2
C ICs on the EVM. Some of the digital control pins
allow control via hardware or software methods. See Section 5.2 for details on these pins and their
operation. The digital control signals can be applied directly to the EVM or by connecting the EVM to a
DSP or micro controller interface board, the
5-6K Interface , or HPA-MCUInterface boards which are
available from Texas Instruments.
5.5.1 Digital Format Control
The ADS1278-SP allows the serial interface to be used in two different formats: an SPI-compatible mode
and a frame-sync format. Switch
S6 is populated with jumpers to select between these two formats:
• SPI format configures the signals as follows:
– The SCLK input of the converter is driven by the serial port signal CLKX, pin J4.3 .
– The signal from the selected source for the clock (see Clock Source ) is connected to the CLKR pin
( J4.5 ) allowing the serial port of a processor to be synchronized to the converters master clock.
– The signal from the selected clock source is routed to the CLK input of the converter.
– Port P10 of the I
2
C port expander U8 is connected to a logic high level, so that the position of
switch S12 can be read back by software.