SNAU133
This board can support the ability to program the FPGA for specific requirements. A standard JTAG connector is
provided for downloading FPGA object code from the Xilinx development environment.
Please note that Texas Instruments does not provide support for any user-designed FPGA functionality beyond the
standard functionality that is shipped with the board.
Hardware Trigger:
The external trigger feature of the Reference Board is designed to enable applications which
trigger a data capture. When the hardware trigger is enabled, an acquisition can be selected from the software, but
the actual beginning of data capture will be postponed until the external trigger pulse is applied to the J26, the
EXT_TRIG SMA.
Note: This only applies to the data which is captured and displayed in the WaveVision GUI; the streaming data to
the FMC connector still runs continuously.
Apply the trigger signal at J26, the EXT_TRIG SMA. If the voltage applied, Vtrigger is less than the threshold,
Vth, of the MC100EP16, then the system will not capture. If Vtrigger is greater than Vth, then a data capture will
occur. Vth is approximately 2.1V, so it is recommended that high trigger voltage is in the range of {2.5V, 3.3V}.
The low trigger voltage should be 0V. Note that this may be a single shot data capture or a continuous trigger. If
the trigger is armed, but Vtrigger is not greater than Vth within approximately 3 minutes, then the software will
time out and show the error message: “Board failed to collect samples.”
Figure 17: Trigger circuit on reference board
1. Connect a signal source to the EXT_TRIG SMA (J26).
2. In the WaveVision5 GUI, select Registers – Settings – check the H/W Trigger box.
3. Select single or continuous capture.
4. Apply Vtrigger above the threshold, Vth, when ready to capture.
Auxiliary Port:
FMC connector forms an auxiliary data port. With it, the FPGA captures the ADC’s high-speed
continuous streaming data and retransmits the data out of the FMC port. See photo below of the FMC port on the
bottom of the board.
•
Install J155 to force FPGA to output data on FMC port (without a power good signal from Carrier to
Mezzanine). This is useful when a non FMC compliant board is connected to Mezzanine
(ADC0XD1520RB)
•
Install J156 to force a power good signal from Mezzanine (ADC0XD1520RB) to Carrier. This is used to
override for initial FPGA debug.
