Texas Instruments ADC DJ 00RF Series, User Manual

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7.2.2 Onboard Clocking Option
All the required clocking is generated on the EVM and no external clock signal is required. The LMK61E2
generates the reference frequency LMK00304 make two copies of the reference signal and sends the one
copy to LMX2594 to generate the sampling clock for the ADC and LMK04828 uses the second copy in clock
distribution mode to provides the FPGA reference clock, FPGA SYSREF signal and ADC SYSREF signal.
Figure
7-2 shows the block diagram of onboard clocking option:
The EVM can be configured to use onboard clocking option with the following steps (see Figure 7-5 ):
• Remove C2 and C3, populate R171 and R174
• Remove C60 and C61, populate C52 and C306
• Uninstall Jumper J13
SYNC
SYSREFREQ
OSCIN RFOUTA
RFOUTB
SDCLKx
SDCLKx
DCLKx
SDCLKx
DA[15:0]
SYNC
FPGA_CLK[3:0]
FPGA_SYSREF
CLKIN0
CLKIN1
LMK61E2
LMK00304
SDCLKx
LMK04828
LMX2594
ADC12DJ5200RF
CLK
SYSREF
DA[15:0]
FMC
SYNC
Board SYNC
Onboard
Clock
/N
SYSR
EF
3
2
.5
MH
z
REFCLK
260 MHz
Figure 7-2. Onboard Clocking System Block Diagram
www.ti.com HSDC Pro Settings for Optional ADC Device Configuration
SLAU640A – APRIL 2019 – REVISED JUNE 2021
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ADCxxDJxx00RF Evaluation Module 19
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