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Tews Technologies TPMC632 Series, User Manual

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Tews Technologies TPMC632 Series User Manual Download Page 30

 

 

TPMC632 User Manual Issue 1.0.6 

Page 30 of 49 

6.2.2  Differential I/O Interface 

Each of the 32 (TPMC632-x1R) or 16 (TPMC632-x2R) differential I/O line pairs is connected on the one side 
with an input, output and output enable pin at the XILINX FPGA. On the other side connected to a 
MAX3078E, an ESD-protected RS485/RS422 transceiver and a 120

Ω

 termination resistor. 

See the following figure for more information of the differential I/O circuitry. 

XILINX

FPGA

FPGA_OUTx

FPGA_OEx

FPGA_INx

120R

MAX3078E

1 Differential Line

X1 / P14

 

Figure 6-3 :  Differential I/O Interface 

6.2.3  Multipoint-LVDS Interface 

Each of the 32 (TPMC632-x3R) or 16 (TPMC632-x4R) M-LVDS I/O line pairs is connected on the one side 
with an input, output and output enable pin at the XILINX FPGA and  on the other side connected to a M-
LVDS transceiver and a 100

Ω

 termination resistor. 

See the following figure for more information of the M-LVDS I/O circuitry. 

XILINX

FPGA

FPGA_OUTx

FPGA_OEx

FPGA_INx

100R

SN65MLVD206

1 M-LVDS Line

X1 / P14

 

Figure 6-4 :  M-LVDS I/O Interface 

Please consider that each TPMC632 M-LVDS line has his own termination. If more than four lines are 
connected together some termination resistors must be removed. 

The actual data transmission rate depends on different factors like  connection, cable  length, fpga 
design etc. 

Summary of Contents for TPMC632 Series

Page 1: ...urable FPGA with 64 TTL I O 32 Differential I O Lines Version 1 0 User Manual Issue 1 0 6 November 2017 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19 e mail info tews com www tews com ...

Page 2: ... 32 TTL and 16 Differential M LVDS Lines XC6SLX100T 2 Spartan 6 FPGA 128 MB DDR3 This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in ...

Page 3: ...rd variants with M LVDS I O buffers are created January 2013 1 0 2 Added chapter Known Issue May 2013 1 0 3 Added DDR3 SDRAM Alternative Part May 2015 1 0 4 Added SPI Flash Alternative Part September 2015 1 0 5 Alternative configurations SPI Flash assembly May 2017 1 0 6 Rename differential I O connector Pins November 2017 ...

Page 4: ... 17 I O Interface 18 4 6 Memory 22 4 7 4 7 1 DDR3 SDRAM 22 4 7 2 SPI Flash 24 User GPIO 25 4 8 On Board Indicators 26 4 9 Thermal Management 26 4 10 5 DESIGN HELP 27 Example Design 27 5 1 6 INSTALLATION 28 Pull Up Voltage 28 6 1 I O Interface 29 6 2 6 2 1 TTL I O Interface 29 6 2 2 Differential I O Interface 30 6 2 3 Multipoint LVDS Interface 30 Back I O Configuration 31 6 3 FPGA Debug Connector 3...

Page 5: ...er Manual Issue 1 0 6 Page 5 of 49 X2 JTAG Header 39 7 4 7 4 1 Connector Type 39 7 4 2 Pin Assignment 39 X3 Debug Connector 40 7 5 7 5 1 Connector Type 40 7 5 2 Pin Assignment 40 8 KNOWN ISSUES 41 9 APPENDIX A 42 ...

Page 6: ...ONS FOR BACK I O OPTIONS 32 FIGURE 6 7 DEBUG CONNECTOR X3 33 FIGURE 6 8 FPGA JTAG CONNECTOR X2 34 FIGURE 7 1 FRONT PANEL I O CONNECTOR NUMBERING 35 List of Tables TABLE 2 1 TECHNICAL SPECIFICATION 9 TABLE 4 1 TPMC632 FPGA FEATURE OVERVIEW 12 TABLE 4 2 FPGA BANK USAGE 12 TABLE 4 3 GTP CONNECTIONS 13 TABLE 4 4 MULTI GIGABIT TRANSCEIVER REFERENCE CLOCKS 13 TABLE 4 5 AVAILABLE FPGA CLOCKS 17 TABLE 4 6...

Page 7: ...e FPGA is configured by a platform flash or SPI flash The flash device is in system programmable An in circuit debugging option is available via a JTAG header for read back and real time debugging of the FPGA design using Xilinx ChipScope The TPMC632 provides either front panel I O via a HD68 SCSI 3 type connector and rear panel I O via P14 User applications for the TPMC632 with XC6SLX45T 2 FPGA c...

Page 8: ...2 FPGA Example DDR3 RAM MT41J64M16 or MT41K64M16 Micron 64 Meg x 16 Bit I O Interface Number of Channels TPMC632 x0R 64 ESD protected TTL lines TPMC632 x1R 32 differential I O lines TPMC632 x2R 32 TTL and 16 differential I O lines TPMC632 x3R 32 M LVDS I O lines TPMC632 x4R 32 TTL and 16 M LVDS I O lines TTL signaling voltage level maximum current 32 mA EIA 422 485 signaling level or M LVDS Standa...

Page 9: ...R 24R 306000 h MTBF values shown are based on calculation according to MIL HDBK 217F and MIL HDBK 217F Notice 2 Environment GB 20 C The MTBF calculation is based on component FIT rates provided by the component suppliers If FIT rates are not available MIL HDBK 217F and MIL HDBK 217F Notice 2 formulas are used for FIT rate calculation Humidity 5 95 non condensing Weight TPMC632 xxR 126 g Table 2 1 ...

Page 10: ...ection 3 1 The TPMC632 is sensitive to static electricity Packing unpacking and all other handling of the TPMC632 has to be done in an ESD EOS protected Area Thermal Considerations 3 2 Forced air cooling is recommended during operation Without forced air cooling damage to the device can occur ...

Page 11: ... 4 1 Bank0 Bank2 Bank 1 Bank 3 Spartan 6 DDR3Bank PCIetoPCI Bridge VCCO 3 3V VCCO 3 3V VCCO 1 5V VCCO 3 3V GTP GPIO DIP Switch LEDs I2C User LEDs DebugHeader SPI Flash User PlatformFlash SPI Flash ExampleDesign Digital I O 64xInput 64xOutput 64xO Enable Config Figure 4 1 FPGA Block Diagram ...

Page 12: ...A Feature Overview The board supports JTAG master serial mode configuration from SPI Flash or SelectMAP configuration from a Platform Flash The FPGA is equipped with 4 I O banks and 4 GTP transceivers Bank VCCO VREF Signals Remarks Bank 0 3 3V none dig I O Interface Bank 1 1 5V 0 75V DDR3 Bank GPIO LED Debug Bank 2 3 3V none dig I O Interface Configuration Bank 3 3 3V none dig I O Interface GTP Ba...

Page 13: ...lock MGTRX D7 C7 MGT1_101 MGTTX B8 A8 not used MGTRX D9 C9 MGT0_123 MGTTX B14 A14 not used MGTRX D13 C13 MGT1_123 MGTTX B16 A16 not used MGTRX D15 C15 Table 4 3 GTP Connections The GTP clock MGT0_101 PCI Express Endpoint Block clock reference of 125 MHz is generated by the SI5338 low jitter clock generator MGT1_101 MGT0_123 and MGT1_123 are not used on the TPMC632 GTP Signal FPGA Pins Connected to...

Page 14: ...electing the Configuration Source Besides direct JTAG configuration the TPMC632 provides two user configuration sources a platform flash and a SPI Flash Both devices share common pins so a selection must be made With the Configuration DIP switch the Configuration source could be selected Set the Configuration DIP Switch S1 to ON the SPI Flash interface is selected with Configuration DIP Switch S1 ...

Page 15: ...ed to access the JTAG chain The JTAG chain can be extended to include the TPMC632 configuration CPLD XCF16 32 XC6SLX T PEX8112 XC2C32 TDI TDO TDI TDO TDI TDO TDI TDO MUX PMC Connector Debug Connector J11 J12 X3 X2 S3 JTAG Header Figure 4 5 JTAG Chain S3 ON Include configuration CPLD to JTAG chain OFF Bypass configuration CPLD default S4 ON Not used OFF Figure 4 6 Configuration DIP Switch Settings ...

Page 16: ... II To use the maximum configuration speed the TPMC632 must be configured to use the 32 MHz external master clock as CCLK To use these configuration feature the configuration option Enable External Master Clock g ExtMasterCclk_en must be enabled Without this option the configuration time for the Spartan6 FPGA exceed the maximum PCI bus setup time TPMC632 1xR configuration devices SPI Flash Winbond...

Page 17: ...ces on the TPMC632 FPGA Clock Pin Name FPGA Pin Number Source Description MGTREFCLK0_101 A10 B10 SI5338 low jitter clock generator 125 MHz PCIe Reference clock IO_L30P_GCLK1_D13_2 Y13 SI5338 low jitter clock generator MCB CLK 62 5 MHz IO_L29N_GCLK2_2 U12 SI5338 low jitter clock generator USER CLK 83 3325 MHz IO_L30N_GCLK0_USERCCLK_2 AB13 32MHz 3 3V oscillator Used for external configuration clock ...

Page 18: ...3 2 FPGA_IN 9 W18 INPUT LVCMOS33 2 FPGA_IN 10 Y17 INPUT LVCMOS33 2 FPGA_IN 11 V15 INPUT LVCMOS33 2 FPGA_IN 12 W17 INPUT LVCMOS33 2 FPGA_IN 13 Y18 INPUT LVCMOS33 2 FPGA_IN 14 V2 INPUT LVCMOS33 3 FPGA_IN 15 Y1 INPUT LVCMOS33 3 FPGA_IN 16 Y14 INPUT LVCMOS33 2 FPGA_IN 17 Y15 INPUT LVCMOS33 2 FPGA_IN 18 B2 INPUT LVCMOS33 0 FPGA_IN 19 C3 INPUT LVCMOS33 0 FPGA_IN 20 A4 INPUT LVCMOS33 0 FPGA_IN 21 D4 INPU...

Page 19: ... 2 8 SLOW FPGA_OE 1 AB16 OUTPUT LVCMOS33 2 8 SLOW FPGA_OE 2 AB11 OUTPUT LVCMOS33 2 8 SLOW FPGA_OE 3 AB8 OUTPUT LVCMOS33 2 8 SLOW FPGA_OE 4 AB10 OUTPUT LVCMOS33 2 8 SLOW FPGA_OE 5 AB7 OUTPUT LVCMOS33 2 8 SLOW FPGA_OE 6 W8 OUTPUT LVCMOS33 2 8 SLOW FPGA_OE 7 AB9 OUTPUT LVCMOS33 2 8 SLOW FPGA_OE 8 R8 OUTPUT LVCMOS33 2 8 SLOW FPGA_OE 9 AB4 OUTPUT LVCMOS33 2 8 SLOW FPGA_OE 10 AB17 OUTPUT LVCMOS33 2 8 SL...

Page 20: ...OW FPGA_OE 50 U8 OUTPUT LVCMOS33 2 8 SLOW FPGA_OE 51 M2 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE 52 T4 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE 53 V5 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE 54 K1 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE 55 N1 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE 56 P5 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE 57 N6 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE 58 K2 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE 59 N7 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE...

Page 21: ...SLOW FPGA_OUT 37 E4 OUTPUT LVCMOS33 3 8 SLOW FPGA_OUT 38 H6 OUTPUT LVCMOS33 3 8 SLOW FPGA_OUT 39 G7 OUTPUT LVCMOS33 3 8 SLOW FPGA_OUT 40 E1 OUTPUT LVCMOS33 3 8 SLOW FPGA_OUT 41 H8 OUTPUT LVCMOS33 3 8 SLOW FPGA_OUT 42 F5 OUTPUT LVCMOS33 3 8 SLOW FPGA_OUT 43 G6 OUTPUT LVCMOS33 3 8 SLOW FPGA_OUT 44 B1 OUTPUT LVCMOS33 3 8 SLOW FPGA_OUT 45 W15 OUTPUT LVCMOS33 2 8 SLOW FPGA_OUT 46 K6 OUTPUT LVCMOS33 3 8...

Page 22: ...P7 A1 A2 G22 SSTL15_II 49 9Ω VTT P3 A2 A3 J20 SSTL15_II 49 9Ω VTT N2 A3 A4 H20 SSTL15_II 49 9Ω VTT P8 A4 A5 M20 SSTL15_II 49 9Ω VTT P2 A5 A6 M19 SSTL15_II 49 9Ω VTT R8 A6 A7 G20 SSTL15_II 49 9Ω VTT R2 A7 A8 E20 SSTL15_II 49 9Ω VTT T8 A8 A9 E22 SSTL15_II 49 9Ω VTT R3 A9 A10 J19 SSTL15_II 49 9Ω VTT L7 A10 AP A11 H19 SSTL15_II 49 9Ω VTT R7 A11 A12 F22 SSTL15_II 49 9Ω VTT N7 A12 BCN A13 G19 SSTL15_II ...

Page 23: ...12 W20 SSTL15_II ODT A7 DQ12 DQ13 W22 SSTL15_II ODT A2 DQ13 DQ14 Y21 SSTL15_II ODT B8 DQ14 DQ15 Y22 SSTL15_II ODT A3 DQ15 LDQS N20 DIFF_SSTL15_II ODT F3 LDQS LDQS N22 DIFF_SSTL15_II ODT G3 LDQS UDQS V21 DIFF_SSTL15_II ODT C7 UDQS UDQS V22 DIFF_SSTL15_II ODT B7 UDQS LDM N19 SSTL15_II ODT E7 LDM UDM P20 SSTL15_II ODT D3 UDM CK K20 DIFF_SSTL15_II 100Ω J7 CK CK L19 DIFF_SSTL15_II K7 CK RZQ F18 SSTL15_...

Page 24: ...ROM the W25Q32JV EEPPROM does not support the QPI mode After configuration it is always accessible from the FPGA so it also can be used for code or user data storage The SPI EEPROM is connected via Quad x4 SPI interface to Spartan6 configuration interface SPI PROM Signal Bank VCCO Pin Description Spartan6 CLK 2 3 3V Y20 Serial Clock CCLK CS 2 3 3V AA3 Chip Select CS0_B DI bit0 2 3 3V AB20 Serial D...

Page 25: ... UART that can work with 1 5V I O voltage should be connected to these signals such as TEWS TA900 A general purpose I O Signal is also connected to the Debug Connector When used with the TEWS TA900 this signal is connected to a Push button and must be configured as FPGA input Signal Bank VCCO Pin Description GPIO_LED0 1 1 5V M16 4x green on board LEDs GPIO_LED1 N15 GPIO_LED2 U19 GPIO_LED3 T20 FPGA...

Page 26: ...es successful FPGA configuration USER 1 USER 2 USER 3 USER 4 Green Green Green Green Design dependent can be controlled by the FPGA Refer to chapter User GPIO Table 4 10 Board Status and User LEDs Thermal Management 4 10 Power dissipation is design dependent Main factors are device utilization frequency and GTP transceiver usage Use the Xilinx XPower Estimator XPE or XPower Analyzer to determine w...

Page 27: ...design covers the main functionalities of the TPMC632 It implements a DMA capable PCIe endpoint with interrupt support register mapping DDR3 memory access and basic I O functions It comes as a Xilinx ISE project with source code and as a ready to download bitstream This example design can be used as a starting point for own projects The basic example design requires the Embedded Development Kit ED...

Page 28: ... Voltage 6 1 The voltage of the pull up resistors can be either 3 3V 5V or alternatively GND specified by jumper J1 The default pull up voltage is 5V Figure 6 1 Pull Up Voltage Jumper Setting J1 Jumper Position Pull Up Voltage 1 3 3 3V 3 5 5V default 4 3 GND 3 4 2 5 1 6 ...

Page 29: ...tput enable can be used to pull the line low or set it in tristate to obtain a high level For example when connecting to a standard 5V CMOS logic input not TTL compatible levels a high level of minimum 3 5V is required Please note that the pull up resistors can only drive high impedance inputs A TVS array protects against ESD shocks See the following figure for more information of the TTL I O circ...

Page 30: ... I O Interface 6 2 3 Multipoint LVDS Interface Each of the 32 TPMC632 x3R or 16 TPMC632 x4R M LVDS I O line pairs is connected on the one side with an input output and output enable pin at the XILINX FPGA and on the other side connected to a M LVDS transceiver and a 100Ω termination resistor See the following figure for more information of the M LVDS I O circuitry XILINX FPGA FPGA_OUTx FPGA_OEx FP...

Page 31: ...ne Back I O connector lines 57 64 can be changed to ground instead of IO_56 IO_63 signals by change of zero ohm resistors The TPMC632 is sensitive to static electricity Packing unpacking and all other handling of the TPMC632 has to be done in an ESD EOS protected Area Figure 6 5 Jumper positions for ground option ...

Page 32: ... default R284 60 ground R287 I O_59 IO_29 default R290 61 ground R277 I O_60 IO_30 default R282 62 ground R278 I O_61 IO_30 default R283 63 ground R275 I O_62 IO_31 default R280 64 ground R276 I O_63 IO_31 default R281 Figure 6 6 Jumper positions for Back I O options Caution Never make simultaneous connections on both jumper positions of one I O line Serious damage of the module is possible ...

Page 33: ...f the signals TDI TDO TMS TCK uses 3 3V I O voltage and can run with up to 6 MHz The FPGA UART consists of Rx and Tx and uses 1 5V I O voltage Communication settings depend on the FPGA programming The General Purpose User Signal uses 1 5V I O voltage When used with the TEWS TA900 this signal is connected to a Push button on the TEWS TA900 and must be configured as FPGA input X3 Figure 6 7 Debug Co...

Page 34: ... and real time debugging of the FPGA design using Xilinx ChipScope A through hole right angle 90 connector with 7 x 2 pins and 2 mm pitch is mounted Molex 0877601416 or compatible With a mounted 2mm pitch flat cable this is of cause a violation of the maximum component height given by the CMC specification be sure that there is enough space to carrier board X1 X2 S1 Figure 6 8 FPGA JTAG Connector ...

Page 35: ...Overview 7 1 X1 X2 X3 P12 P11 P14 S1 J1 X1 Front Panel I O Connector 7 2 TPMC632 Pin68 Pin35 Pin1 Pin34 Figure 7 1 Front Panel I O Connector Numbering 7 2 1 Connector Type Pin Count 68 Connector Type HD68 SCSI 3 type female connector Source Order Info AMP 787082 7 or compatible ...

Page 36: ..._27 IO_13 IO_13 16 IO_28 IO_14 IO_14 50 IO_29 IO_14 IO_14 17 IO_30 IO_15 IO_15 51 IO_31 IO_15 IO_15 18 IO_32 IO_16 IO_32 52 IO_33 IO_16 IO_33 19 IO_34 IO_17 IO_34 53 IO_35 IO_17 IO_35 20 IO_36 IO_18 IO_36 54 IO_37 IO_18 IO_37 21 IO_38 IO_19 IO_38 55 IO_39 IO_19 IO_39 22 IO_40 IO_20 IO_40 56 IO_41 IO_20 IO_41 23 IO_42 IO_21 IO_42 57 IO_43 IO_21 IO_43 24 IO_44 IO_22 IO_44 58 IO_45 IO_22 IO_45 25 IO_...

Page 37: ... 10 IO_9 IO_4 IO_4 42 IO_41 IO_20 IO_41 11 IO_10 IO_5 IO_5 43 IO_42 IO_21 IO_42 12 IO_11 IO_5 IO_5 44 IO_43 IO_21 IO_43 13 IO_12 IO_6 IO_6 45 IO_44 IO_22 IO_44 14 IO_13 IO_6 IO_6 46 IO_45 IO_22 IO_45 15 IO_14 IO_7 IO_7 47 IO_46 IO_23 IO_46 16 IO_15 IO_7 IO_7 48 IO_47 IO_23 IO_47 17 IO_16 IO_8 IO_8 49 IO_48 IO_24 IO_48 18 IO_17 IO_8 IO_8 50 IO_49 IO_24 IO_49 19 IO_18 IO_9 IO_9 51 IO_50 IO_25 IO_50 ...

Page 38: ...e 38 of 49 Pin x0R x1R x3R x2R x4R Pin x0R x1R x3R x2R x4R 30 IO_29 IO_14 IO_14 62 IO_61 IO_30 IO_61 31 IO_30 IO_15 IO_15 63 IO_62 IO_31 IO_62 32 IO_31 IO_15 IO_15 64 IO_63 IO_31 IO_63 Table 7 2 Pin Assignment Back I O PMC Connector P14 ...

Page 39: ...Pin Count 14 Connector Type 2 00 mm Pitch Milli Grid Header Source Order Info Molex 877601416 or compatible 7 4 2 Pin Assignment Pin Signal Description 1 NC Not Connected 2 VREF JTAG Reference Voltage 3 3V 3 GND Ground 4 TMS Test Mode Select Input 5 GND Ground 6 TCK Test Clock 7 GND Ground 8 TDO Test Data Output TAP Controller TDI 9 GND Ground 10 TDI Test Data Input TAP Controller TDO 11 GND not c...

Page 40: ...put Input at JTAG Interface 4 GND Ground 5 TDI I Test Data Input Output at JTAG Interface 6 TMS I Test Mode Select Input 7 GND Ground 8 TCK I Test Clock 9 GND Ground 10 UART_RxD I FPGA UART Receive Data Input 11 1 5V O UART reference I O voltage 12 UART_TxD O FPGA UART Transmit Data Output 13 GND Ground 14 NC Not used on TPMC632 15 NC Not used on TPMC632 16 NC Not used on TPMC632 17 GND Ground 18 ...

Page 41: ...s time the I O lines of the TPMC632 may randomly toggle between high and low in case that I O Line 19 of the TPMC632 X1 pin 45 resp P14 pin 20 is low As long as the TPMC632 is used with J1 configured as a Pull up and I O Line 19 is not connected to GND or driven low externally this issue does not occur To avoid this issue the TPMC632 xxR I O Line 19 should have a minimum of 2V DC lower limit of TT...

Page 42: ...xed GPIO LED location constraints Corrected constraints for FPGA_IN 29 FPGA_IN 30 and FPGA_OUT 25 Version 3 SE 25 10 2011 Adapted pin locations to post layout results Version 4 SE 02 12 2011 File Rename Revised Header Version 5 SE 13 12 2011 Added driver strength and slew rate on I O lines for improved signal integrity Version 6 SE 11 01 2012 Updated pin bank affiliation comment for FPGA_OE and FP...

Page 43: ...fine I O Standard net FPGA_OE iostandard LVCMOS33 Bank 0 2 3 Supply 3 3V net FPGA_IN iostandard LVCMOS33 Bank 0 2 3 Supply 3 3V net FPGA_OUT iostandard LVCMOS33 Bank 2 3 Supply 3 3V I O Standard Enhancement net FPGA_OE slow drive 8 Settings for Signal Integrity net FPGA_OUT slow drive 8 Settings for Signal Integrity Define Location Constraints net FPGA_OE 0 loc T15 Bank 2 net FPGA_OE 1 loc AB16 Ba...

Page 44: ...3 net FPGA_OE 44 loc U3 Bank 3 net FPGA_OE 45 loc U4 Bank 3 net FPGA_OE 46 loc T3 Bank 3 net FPGA_OE 47 loc P6 Bank 3 net FPGA_OE 48 loc R7 Bank 3 net FPGA_OE 49 loc M7 Bank 3 net FPGA_OE 50 loc U8 Bank 2 net FPGA_OE 51 loc M2 Bank 3 net FPGA_OE 52 loc T4 Bank 3 net FPGA_OE 53 loc V5 Bank 3 net FPGA_OE 54 loc K1 Bank 3 net FPGA_OE 55 loc N1 Bank 3 net FPGA_OE 56 loc P5 Bank 3 net FPGA_OE 57 loc N6...

Page 45: ...oc C4 Bank 0 net FPGA_IN 44 loc G13 Bank 0 net FPGA_IN 45 loc G15 Bank 0 net FPGA_IN 46 loc D17 Bank 0 net FPGA_IN 47 loc E16 Bank 0 net FPGA_IN 48 loc G16 Bank 0 net FPGA_IN 49 loc F17 Bank 0 net FPGA_IN 50 loc D18 Bank 0 net FPGA_IN 51 loc D19 Bank 0 net FPGA_IN 52 loc F15 Bank 0 net FPGA_IN 53 loc F9 Bank 0 net FPGA_IN 54 loc C19 Bank 0 net FPGA_IN 55 loc F7 Bank 0 net FPGA_IN 56 loc G11 Bank 0...

Page 46: ...8 loc H6 Bank 3 net FPGA_OUT 39 loc G7 Bank 3 net FPGA_OUT 40 loc E1 Bank 3 net FPGA_OUT 41 loc H8 Bank 3 net FPGA_OUT 42 loc F5 Bank 3 net FPGA_OUT 43 loc G6 Bank 3 net FPGA_OUT 44 loc B1 Bank 3 net FPGA_OUT 45 loc W15 Bank 2 net FPGA_OUT 46 loc K6 Bank 3 net FPGA_OUT 47 loc P8 Bank 3 net FPGA_OUT 48 loc R9 Bank 2 net FPGA_OUT 49 loc V11 Bank 2 net FPGA_OUT 50 loc Y10 Bank 2 net FPGA_OUT 51 loc P...

Page 47: ...2 Bank 1 net DDR_A 10 loc J19 Bank 1 net DDR_A 11 loc H19 Bank 1 net DDR_A 12 loc F22 Bank 1 net DDR_A 13 loc G19 Bank 1 net DDR_A 14 loc F20 Bank 1 net DDR_BA 0 loc K17 Bank 1 net DDR_BA 1 loc L17 Bank 1 net DDR_BA 2 loc K18 Bank 1 net DDR_CK_P loc K20 Bank 1 net DDR_CK_N loc L19 Bank 1 net DDR_DQ 0 loc R20 Bank 1 net DDR_DQ 1 loc R22 Bank 1 net DDR_DQ 2 loc P21 Bank 1 net DDR_DQ 3 loc P22 Bank 1...

Page 48: ...oc AB13 Bank 2 net MCB_CLK loc Y13 Bank 2 net USER_CLK loc U12 Bank 2 net USER_TCLK loc T12 Bank 2 Additional Constraints net USER_CCLK tnm_net USER_CCLK timespec TS_USER_CCLK period USER_CCLK 32 MHz high 50 net MCB_CLK tnm_net MCB_CLK timespec TS_MCB_CLK period USER_MCB_CLK 62 5 MHz high 50 net USER_CLK tnm_net USER_CLK timespec TS_USER_CLK period USER_CLK 83 3325 MHz high 50 net USER_TCLK tnm_ne...

Page 49: ...MOS15 Bank 1 Supply 1 5V net GPIO_T iostandard LVCMOS15 Bank 1 Supply 1 5V net GPIO_EN iostandard LVCMOS15 Bank 1 Supply 1 5V Location Constraints net GPIO_LED 0 loc M16 Bank 1 net GPIO_LED 1 loc N15 Bank 1 net GPIO_LED 2 loc U19 Bank 1 net GPIO_LED 3 loc T20 Bank 1 net GPIO_TCK loc M17 Bank 1 net GPIO_TMS loc M18 Bank 1 net GPIO_TDI loc R15 Bank 1 net GPIO_TDO loc R16 Bank 1 net GPIO_EN loc P18 B...

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