TPCE636 User Manual Issue 1.0.2
Page 27 of 104
5.2.10 User FPGA Configuration Data Register - 0xD4
Bit
Symbol
Description
Access
Reset
Value
31:0
ISP_FP_DAT
ISP Select Map Write Data
Write Data Register for direct Slave Select Map
FPGA programming mode
Must be written with 32-bit FPGA programming
data until the FPGA Done pin goes high (after the
actual programming data, writing some dummy
data may be required).
W
-
Table 5-14 : User FPGA Configuration Data Register
The User FPGA Configuration Data Register is used to write data within the User FPGA Slave Select Map
Configuration directly to the User FPGA.
5.2.11 ISP Control Register - 0xE0
Bit
Symbol
Description
Access
Reset
Value
31:1
Reserved
0
0
ISP_EN
ISP Mode Enable
0: Disable ISP Mode
1: Enable ISP Mode
This bit controls the BCC interface between BCC,
SPI-Flash and the User FPGA (Kintex-7).
When set, the BCC is both SPI Flash Master and
FPGA Configuration Interface Master.
Must be set to 1 for direct Slave Select Map mode or
SPI Flash programming.
Must be set to 0 when the User FPGA should
configure from the SPI Flash (e.g. after SPI Flash
programming) in ‘Master Serial / SPI’ mode.
Note, that for ISP Direct FPGA Programming, the
FPGA must first be set to Slave Select Map
configuration mode.
R/W
0
Table 5-15 : ISP Control Register
