Tews Technologies TPCE636, User Manual

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TPCE636 User Manual Issue 1.0.2 Page 26 of 104
5.2.8 Interrupt Status Register - 0xC4
Bit Symbol Description Access
Reset
Value
31:2 Reserved 0
1
ISP_INS_IS
ISP SPI Instruction Done Event Interrupt Status
When set, the PCI INTA# interrupt is asserted.
The Interrupt is cleared by writing a ‘1’.
0: Interrupt not active or disabled
1: Interrupt active and enabled
R/C
0
0 ISP_DAT_IS
ISP SPI Page Data Done Event Interrupt Status
When set, the PCI INTA# interrupt is asserted.
The Interrupt is cleared by writing a ‘1’.
0: Interrupt not active or disabled
1: Interrupt active and enabled
R/C 0
Table 5-12 : Interrupt Status Register
5.2.9 User FPGA Configuration Control/Status Register - 0xD0
Bit Symbol Description Access
Reset
Value
31:5 Reserved 0
4 K7_LINK_ENA
1: Kintex-7 to PCIe-Switch LINK is enabled
0: Kintex-7 to PCIe-Switch LINK is disabled
R/W 1
3 FP_INIT_STAT
User FPGA INIT_B Pin Status
0: FPGA INIT_B Pin Level is Low (active)
1: FPGA INIT_B Pin Level is High (not active)
R x
2 FP_DONE_STAT
User FPGA DONE Pin Status
The FPGA Done pin is high in case of successful
FPGA configuration.
0: FPGA DONE Pin Level is Low (not active)
1: FPGA DONE Pin Level is High (active)
R x
1 FP_RE_CFG
After power-up the FPGA automatically configures
from the on-board SPI Flash in ‘Master Serial /
SPI’ mode.
User FPGA Re-Configuration
1: Set all FPGA I/O pins to High-Z and prepare a
User FPGA Re-Configuration
1

0: Start User FPGA Re-Configuration
R/W 0
0 FP_CFG_MD
Set User FPGA Configuration Mode
0: Master Serial / SPI
1: Slave SelectMap (Parallel)
After power-up the User FPGA automatically
configures from the on-board SPI Flash in ‘Master
Serial / SPI’ mode.
R/W 0
Table 5-13 : User FPGA Configuration Control/Status Register