Tews Technologies TPCE636, User Manual

Page: 15 / 104

TPCE636 User Manual Issue 1.0.2 Page 15 of 104
4.2.2.1 Local Configuration Register Space
Offset to PCI
Base Address
Register Name Size (Bit)
0x00 DAC Control and Status Register 32
0x04 DAC Output Voltage Range Register 32
0x08 – 0x0C Reserved -
0x10 Register for VOFF and VREF of DAC Channel 1 32
0x14 Register for VOFF and VREF of DAC Channel 2 32
0x18 Register for VOFF and VREF of DAC Channel 3 32
0x1C Register for VOFF and VREF of DAC Channel 4 32
0x20 Register for VOFF and VREF of DAC Channel 5 32
0x24 Register for VOFF and VREF of DAC Channel 6 32
0x28 Register for VOFF and VREF of DAC Channel 7 32
0x2C Register for VOFF and VREF of DAC Channel 8 32
0x30 Register for VOFF and VREF of DAC Channel 9 32
0x34 Register for VOFF and VREF of DAC Channel 10 32
0x38 Register for VOFF and VREF of DAC Channel 11 32
0x3C Register for VOFF and VREF of DAC Channel 12 32
0x40 Register for VOFF and VREF of DAC Channel 13 32
0x44 Register for VOFF and VREF of DAC Channel 14 32
0x48 Register for VOFF and VREF of DAC Channel 15 32
0x4C Register for VOFF and VREF of DAC Channel 16 32
0x50 – 0x7F Reserved -
0x80 Kintex-7 JTAG Control Register 32
0x84 Kintex-7 JTAG Interface Register 32
0x88 Kintex-7 JTAG Signal TMS Data Register 32
0x8C Kintex-7 JTAG Signal TDI Data Register 32
0x90 Kintex-7 JTAG Signal TDO Data Register 32
0x94 – 0x9F Reserved -
0xA0 I2C Bridge Register 32
0xA4 – 0xBF Reserved -
0xC0 Interrupt Enable Register 32
0xC4 Interrupt Status Register 32
0xC8 Reserved -
0xCC Reserved -
0xD0 User FPGA Configuration Control/Status Register 32
0xD4 User FPGA Configuration Data Register (Slave SelectMAP) 32
0xD8 Reserved -
0xDC Reserved -
0xE0 ISP Control Register (SPI) 32