TAMC900 User Manual Issue 2.0.1
Page 48 of 71
11 Clock Distribution
The TAMC900 has several Clock sources:
•
3 Clock Inputs from the SiCA
•
1 Clock Input from AMC interface connector
•
2 local Clocks
•
2 Clock outputs of the FPGA
The Clocks are distributed to the ADCs and the FPGA. Configuration of the Clock Distribution is done via the
on board CPLD. Refer to the CPLD registers description for programming details.
FPGA
Clock 1
Clock 2
Clock 3
AMC-Clock
1:3
4 x 4
Crosspoint
Switch
MGT
2:5
2:5
ADC 0 *
ADC 1 *
ADC 2 *
ADC 3 *
ADC 4 *
ADC 5 *
ADC 6 *
ADC 7 *
Local Clocks
Golbal
Clock
Buffer
SY89540U
ICS85314-11
ICS85314-11
ICS874003-02
* = Differential to LVTTL conversion
of the ADC clock signals is done by
MC100ES60T23 devices
MGT_CLK
GCLK
SW_CLK0
CL
K
O
UT
0
CL
K
O
UT
1
LC
LK
_250
MUX0_FB
MUX1_FB
S
W
_C
LK
O
U
T
_0
S
W
_C
LK
O
U
T
_1
SW_CLKOUT_2
SW_CLKOUT_3
LC
LK
_50
Figure 11-1: Clock Distribution Block Diagram
The external clock inputs “Clock 1”, “Clock 2” and “Clock 3” are LVDS compatible.
“AMC Clock” is the FCLKA signal from the AMC connector, routed through a jitter attenuator (ICS874003-02)
to achieve a max. Jitter below 40ps even if the original FCLKA has much more jitter. In most systems,
FCLKA is a 100 MHz PCI-Express reference clock that may be a SSC (Spread Spectrum Clock)